| /u-boot/include/ |
| A D | k3-clk.h | 100 #define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \ argument
104 .reg = _reg, \
109 #define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags, _div_flags) \ argument
113 .name = _name, .parent = _parent, .reg = _reg, \
118 #define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _div_flags, _freq) \ argument
123 .name = _name, .parent = _parent, .reg = _reg, \
128 #define CLK_PLL(_name, _parent, _reg, _flags) \ argument
131 .clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \
134 #define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq) \ argument
139 .reg = _reg, .flags = _flags } \
[all …]
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| A D | regmap.h | 479 #define REG_FIELD(_reg, _lsb, _msb) { \ argument
480 .reg = _reg, \
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| /u-boot/drivers/clk/uniphier/ |
| A D | clk-uniphier.h | 59 #define UNIPHIER_CLK_GATE(_id, _parent, _reg, _bit) \ argument
65 .reg = (_reg), \
70 #define UNIPHIER_CLK_GATE_SIMPLE(_id, _reg, _bit) \ argument
71 UNIPHIER_CLK_GATE(_id, UNIPHIER_CLK_ID_INVALID, _reg, _bit)
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| /u-boot/drivers/pinctrl/mtmips/ |
| A D | pinctrl-mtmips-common.h | 45 #define GRP(_name, _funcs, _reg, _shift, _mask) \ argument
46 { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
49 #define GRP_PCONF(_name, _funcs, _reg, _shift, _mask, _pconf_reg, _pconf_shift) \ argument
50 { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mtk.h | 129 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \ argument
132 .mux_reg = _reg, \
135 .gate_reg = _reg, \
142 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ argument
143 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
145 #define MUX(_id, _parents, _reg, _shift, _width) { \ argument
147 .mux_reg = _reg, \
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| A D | clk-mt7986.c | 373 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
375 .id = _id, .mux_reg = (_reg) + 0x8, \
376 .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
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| A D | clk-mt7981.c | 383 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
385 .id = _id, .mux_reg = (_reg) + 0x8, \
386 .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
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| A D | clk-mt7629.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
36 .reg = _reg, \
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| A D | clk-mt8512.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
25 .reg = _reg, \
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| A D | clk-mt8516.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
24 .reg = _reg, \
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| A D | clk-mt7622.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
36 .reg = _reg, \
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| A D | clk-mt8183.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \ argument
25 .reg = _reg, \
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| A D | clk-mt7623.c | 29 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
32 .reg = _reg, \
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| A D | clk-mt8518.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
24 .reg = _reg, \
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| /u-boot/include/linux/ |
| A D | bitfield.h | 52 #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ argument
60 BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
101 #define FIELD_GET(_mask, _reg) \ argument
103 __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
104 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
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| /u-boot/arch/arm/include/asm/mach-imx/ |
| A D | regs-common.h | 61 struct mxs_register_8 name##_reg; \
67 struct mxs_register_32 name##_reg; \
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| /u-boot/drivers/clk/meson/ |
| A D | clk_meson.h | 19 #define MESON_GATE(id, _reg, _bit) \ argument
21 .reg = (_reg), \
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| /u-boot/drivers/reset/ |
| A D | sti-reset.c | 83 #define STIH407_SRST_CORE(_reg, _bit) \ argument
84 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
86 #define STIH407_SRST_SBC(_reg, _bit) \ argument
87 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
89 #define STIH407_SRST_LPM(_reg, _bit) \ argument
90 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
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| A D | reset-uniphier.c | 33 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
36 .reg = (_reg), \
40 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
43 .reg = (_reg), \
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| /u-boot/drivers/clk/renesas/ |
| A D | rcar-cpg-lib.c | 35 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) argument
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| A D | r9a06g032-clocks.c | 46 #define RB(_reg, _bit) ((struct regbit) { \ argument
47 .reg = (_reg) / 4, \
184 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \ argument
189 .reg = _reg, \
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| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | clk.c | 186 static inline void set_val(u32 _reg, u32 _mask, u32 _val) in set_val() argument
190 writel((readl(pll_regs + _reg) & (~(_mask))) | _val, pll_regs + _reg); in set_val()
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| /u-boot/drivers/pinctrl/nuvoton/ |
| A D | pinctrl-npcm8xx.c | 288 #define FUNC(_name, _reg, _bit, ...) \ argument
294 #define FUNC(_name, _reg, _bit, ...) \ argument
302 #define FUNC(_name, _reg, _bit, ...) { \ argument
307 .reg = _reg, \
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