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/u-boot/arch/riscv/lib/
A Dmemcpy.S14 mv t6, a0
22 add t0, a0, a2
40 beq a0, a2, 2f
44 sb a5, 0(a0)
45 addi a0, a0, 1
46 bne a0, a2, 1b
94 addi a0, a0, 16*SZREG
106 addi a0, a0, SZREG
120 addi a0, a0, 1
124 mv a0, t6
[all …]
A Dmemmove.S19 sub t0, a0, a1
30 mv t0, a0
31 add a0, a0, a2
49 beq a0, a2, 2f
53 addi a0, a0, -1
54 sb a5, 0(a0)
72 addi a0, a0, -SZREG
86 addi a0, a0, -1
87 sb a5, 0(a0)
91 mv a0, t0
[all …]
A Dsetjmp.S10 #define STORE_IDX(reg, idx) sd reg, (idx*8)(a0)
11 #define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0)
13 #define STORE_IDX(reg, idx) sw reg, (idx*4)(a0)
14 #define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0)
34 li a0, 0
57 seqz a0, a1
58 add a0, a0, a1
A Dcrt0_riscv_efi.S161 SAVE_LONG(a0, 0)
165 lla a0, ImageBase
168 bne a0, zero, 0f
171 LOAD_LONG(a0, 0)
/u-boot/arch/mips/mach-octeon/
A Dlowlevel_init.S24 dmfc0 a0, COP0_CVMMEMCTL_REG
25 dins a0, zero, 0, 9
36 dmtc0 a0, COP0_CVMMEMCTL_REG
39 dmfc0 a0, COP0_CVMCTL_REG
41 dmtc0 a0, COP0_CVMCTL_REG
70 ld a0, 0(t0)
74 sd a0, 0(t1)
113 dmfc0 a0, COP0_CVMMEMCTL_REG
114 dins a0, zero, 0, 9
116 dmtc0 a0, COP0_CVMMEMCTL_REG
[all …]
/u-boot/arch/mips/mach-mtmips/mt7628/
A Dlowlevel_init.S69 li a0, 0
74 1: cache INDEX_STORE_TAG_I, 0(a0)
75 addiu a0, CONFIG_SYS_ICACHE_LINE_SIZE
76 bne a0, a1, 1b
80 li a0, 0
85 2: cache INDEX_STORE_TAG_D, 0(a0)
86 addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE
87 bne a0, a1, 2b
104 and t0, a0, a2
108 cache INDEX_STORE_TAG_D, 0(a0)
[all …]
/u-boot/arch/xtensa/cpu/
A Dstart.S82 movi a0, 0
227 movi a0, 0
296 callx0 a0
303 ssl a0
304 movi a0, 1
305 sll a0, a0
361 callx0 a0
455 addx4 a0, a2, a0
456 l32i a0, a0, 0
459 callx0 a0
[all …]
/u-boot/arch/riscv/cpu/
A Dstart.S51 mv tp, a0
103 mv a0, sp
110 mv s0, a0
118 mv sp, a0
219 mv s0, a0
240 beqz a0, 1f
241 mv a1, a0
251 mv a0, zero
375 beqz a0, 1f
376 mv a1, a0
[all …]
/u-boot/drivers/rng/
A Dsmccc_trng.c106 switch (res.a0) { in smccc_trng_read()
131 static bool smccc_trng_is_supported(void (*invoke_fn)(unsigned long a0, unsigned long a1, in smccc_trng_is_supported() argument
140 if (res.a0 == ARM_SMCCC_RET_NOT_SUPPORTED) in smccc_trng_is_supported()
144 if (res.a0 & BIT(31)) in smccc_trng_is_supported()
151 if (res.a0 == ARM_SMCCC_RET_TRNG_NOT_SUPPORTED) in smccc_trng_is_supported()
155 return res.a0 == ARM_SMCCC_RET_TRNG_SUCCESS; in smccc_trng_is_supported()
175 priv->smc64 = (res.a0 == ARM_SMCCC_RET_TRNG_SUCCESS); in smccc_trng_probe()
179 if (res.a0 != ARM_SMCCC_RET_TRNG_NOT_SUPPORTED) { in smccc_trng_probe()
180 unsigned long uuid_a0 = res.a0; in smccc_trng_probe()
187 major = (res.a0 & TRNG_MAJOR_MASK) >> TRNG_MAJOR_SHIFT; in smccc_trng_probe()
[all …]
/u-boot/board/imgtec/boston/
A Dlowlevel_init.S25 PTR_LA a0, msg_ddr_cal
33 PTR_LA a0, msg_ddr_ok
44 ld k1, 0(a0)
47 lw k1, 0(a0)
49 lw k1, 4(a0)
/u-boot/arch/mips/mach-ath79/qca956x/
A Dqca956x-ddr-tap.S18 li a0, 0xbd001f00
20 sw zero, 0x4(a0) /* Place where the number of passing taps are saved. */
21 sw zero, 0x14(a0) /* Place where the last pass tap value is stored */
23 sw a1, 0x10(a0) /* Place where the First pass tap value is stored */
26 li a0, CKSEG1ADDR(AR71XX_RESET_BASE) /* RESET_BASE_ADDRESS */
27 lw a1, 0x1c(a0) /* Reading the RST_RESET_ADDRESS */
30 sw a1, 0x1c(a0)
35 sw a1, 0x1c(a0) /* Taking the RTC out of RESET */
38 li a0, CKSEG1ADDR(QCA956X_RTC_BASE) /* RTC_BASE_ADDRESS */
40 sw a1, 0x0040(a0) /* RTC_SYNC_RESET_ADDRESS */
[all …]
/u-boot/arch/m68k/cpu/mcf532x/
A Dstart.S20 moveml %d0-%d7/%a0-%a6,%sp@;
117 move.w (%a0), %d0
120 move.w %d0, (%a0)
187 move.l %a0, %a3
199 move.l %a0, %a1
209 move.l %a0, %a1
211 move.l %a0, %d1
221 move.l %a0, %a1
225 move.l %a0, %a2
231 add.l %a0,%d1
[all …]
/u-boot/fs/zfs/
A Dzfs_fletcher.c40 uint64_t a0, b0, a1, b1; in fletcher_2_endian() local
42 for (a0 = b0 = a1 = b1 = 0; ip < ipend; ip += 2) { in fletcher_2_endian()
43 a0 += zfs_to_cpu64(ip[0], endian); in fletcher_2_endian()
45 b0 += a0; in fletcher_2_endian()
49 zcp->zc_word[0] = cpu_to_zfs64(a0, endian); in fletcher_2_endian()
/u-boot/arch/m68k/cpu/mcf5445x/
A Dstart.S275 jmp (%a0)
311 jmp (%a0)
423 jmp (%a0)
528 move.l %a0, %a3
540 move.l %a0, %a1
550 move.l %a0, %a1
552 move.l %a0, %d1
562 move.l %a0, %a1
566 move.l %a0, %a2
572 add.l %a0,%d1
[all …]
/u-boot/arch/mips/mach-mtmips/mt7621/spl/
A Dlaunch_ll.S35 sll t1, a0
53 bne t2, a0, _next_coherent_core
66 li a0, KSEG0ADDR(CPULAUNCH)
68 addu a0, t1
72 sw t0, LAUNCH_FLAGS(a0)
93 move t0, a0
125 lw a0, LAUNCH_A0(t0)
159 addu t1, t0, a0
196 li a0, 2
214 beqz a0, _vpe1_init_done
[all …]
A Dstart.S168 la a0, __text_start
169 move a1, a0
173 ins a0, a3, 29, 3 # convert to KSEG1
192 la a0, __bss_start
194 1: sw zero, 0(a0)
195 addiu a0, 4
196 ble a0, a1, 1b
222 move a0, zero # a0 <-- boot_flags = 0
/u-boot/arch/arm/mach-tegra/
A Dpmc.c60 if (res.a0) in tegra_pmc_readl()
61 printf("%s(): SMC failed: %lu\n", __func__, res.a0); in tegra_pmc_readl()
78 if (res.a0) in tegra_pmc_writel()
79 printf("%s(): SMC failed: %lu\n", __func__, res.a0); in tegra_pmc_writel()
/u-boot/arch/m68k/cpu/mcf52x2/
A Dstart.S18 moveml %d0-%d7/%a0-%a6,%sp@; \
142 move.l (%a0)+, (%a2)+
143 cmp.l %a0, %a1
251 move.l %a0, %a3
262 move.l %a0, %a1
272 move.l %a0, %a1
274 move.l %a0, %d1
284 move.l %a0, %a1
288 move.l %a0, %a2
294 add.l %a0,%d1
[all …]
/u-boot/arch/m68k/cpu/mcf530x/
A Dstart.S18 moveml %d0-%d7/%a0-%a6,%sp@
22 moveml %sp@,%d0-%d7/%a0-%a6;
176 move.l %a0, %a3
187 move.l %a0, %a1
197 move.l %a0, %a1
199 move.l %a0, %d1
209 move.l %a0, %a1
215 move.l %a0, %a2
221 add.l %a0,%d1
227 move.l %a0, %a1
[all …]
/u-boot/arch/m68k/cpu/mcf523x/
A Dstart.S17 moveml %d0-%d7/%a0-%a6,%sp@;
20 moveml %sp@,%d0-%d7/%a0-%a6; \
172 move.l %a0, %a3
184 move.l %a0, %a1
194 move.l %a0, %a1
196 move.l %a0, %d1
206 move.l %a0, %a1
210 move.l %a0, %a2
216 add.l %a0,%d1
222 move.l %a0, %a1
[all …]
/u-boot/include/linux/
A Darm-smccc.h67 unsigned long a0; member
93 bool (*is_supported)(void (*invoke_fn)(unsigned long a0, unsigned long a1, unsigned long a2,
114 asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1,
131 asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
/u-boot/arch/mips/lib/
A Dcache_init.S93 li a0, \mode
268 PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
269 PTR_ADDU a1, a0, v0
270 2: PTR_ADDIU a0, 64
271 f_fill64 a0, -64, zero
272 bne a0, a1, 2b
430 ins t0, a0, 0, 3
432 xor a0, a0, t0
433 andi a0, a0, CONF_CM_CMASK
434 xor a0, a0, t0
[all …]
A Dgenex.S137 mfc0 a0, CP0_STATUS
138 ori a0, STATMASK
139 xori a0, STATMASK
140 mtc0 a0, CP0_STATUS
142 and a0, v1
146 or v0, a0
190 move a0, sp
211 move a0, sp
/u-boot/board/phytium/pomelo/
A Dpll.c42 return res.a0; in get_reset_source()
52 if (res.a0 != 0) in pll_init()
53 panic("PLL init failed :0x%lx\n", res.a0); in pll_init()
/u-boot/drivers/firmware/
A Dpsci.c67 res.a0 = PSCI_RET_DISABLED; in invoke_psci_fn()
68 return res.a0; in invoke_psci_fn()
100 static void smccc_invoke_hvc(unsigned long a0, unsigned long a1, in smccc_invoke_hvc() argument
106 arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res); in smccc_invoke_hvc()
109 static void smccc_invoke_smc(unsigned long a0, unsigned long a1, in smccc_invoke_smc() argument
115 arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res); in smccc_invoke_smc()

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