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/u-boot/board/sysam/stmark2/
A Dsbf_dram_init.S25 move.l #PPMCR0, %a1
26 move.b #46, (%a1)
29 move.l #MSCR_SDRAMC, %a1
30 move.b #1, (%a1)
48 move.l #MISCCR2, %a1
49 move.w #0xa01d, (%a1)
52 move.l #DDR_RCR, %a1
60 move.l #DDR_PADCR, %a1
63 move.l #DDR_CR00, %a1
69 move.l #DDR_CR06, %a1
[all …]
/u-boot/arch/riscv/lib/
A Dmemset.S29 sb a1, 0(t0)
36 andi a1, a1, 0xff
37 slli a3, a1, 8
38 or a1, a3, a1
39 slli a3, a1, 16
40 or a1, a3, a1
42 slli a3, a1, 32
43 or a1, a3, a1
67 REG_S a1, 0(t0)
68 REG_S a1, SZREG(t0)
[all …]
A Dmemcpy.S12 beq a0, a1, .copy_end
42 lb a5, 0(a1)
43 addi a1, a1, 1
88 addi a1, a1, 16*SZREG
103 REG_L a5, 0(a1)
104 addi a1, a1, SZREG
117 lb a5, 0(a1)
118 addi a1, a1, 1
141 andi a1, a1, ~(SZREG-1)
149 addi a1, a1, SZREG
[all …]
A Dmemmove.S19 sub t0, a0, a1
32 add a1, a1, a2
51 addi a1, a1, -1
52 lb a5, 0(a1)
70 addi a1, a1, -SZREG
71 REG_L a5, 0(a1)
84 addi a1, a1, -1
85 lb a5, 0(a1)
107 andi a1, a1, ~(SZREG-1)
114 addi a1, a1, -SZREG
[all …]
A Dcrt0_riscv_efi.S162 SAVE_LONG(a1, 1)
166 lla a1, _DYNAMIC
170 LOAD_LONG(a1, 1)
/u-boot/arch/m68k/cpu/mcf5445x/
A Dstart.S483 jsr (%a1)
492 jsr (%a1)
496 jsr (%a1)
501 jsr (%a1)
533 cmp.l %a1,%a2
540 move.l %a0, %a1
542 jmp (%a1)
555 clr.l (%a1)+
556 cmp.l %a1,%d1
574 cmp.l %a2, %a1
[all …]
/u-boot/arch/m68k/cpu/mcf530x/
A Dstart.S136 jsr (%a1)
145 jsr (%a1)
149 jsr (%a1)
154 jsr (%a1)
180 cmp.l %a1,%a2
189 jmp (%a1)
202 clr.l (%a1)+
203 cmp.l %a1,%d1
233 jsr (%a1)
247 jsr (%a1)
[all …]
/u-boot/arch/m68k/cpu/mcf532x/
A Dstart.S142 jsr (%a1)
151 jsr (%a1)
155 jsr (%a1)
160 jsr (%a1)
192 cmp.l %a1,%a2
199 move.l %a0, %a1
201 jmp (%a1)
214 clr.l (%a1)+
215 cmp.l %a1,%d1
233 cmp.l %a2, %a1
[all …]
/u-boot/arch/m68k/cpu/mcf523x/
A Dstart.S127 jsr (%a1)
136 jsr (%a1)
140 jsr (%a1)
145 jsr (%a1)
177 cmp.l %a1,%a2
184 move.l %a0, %a1
186 jmp (%a1)
199 clr.l (%a1)+
200 cmp.l %a1,%d1
218 cmp.l %a2, %a1
[all …]
/u-boot/arch/xtensa/cpu/
A Dstart.S292 mov a1, a2
382 addi a1, a1, -16 - 4 # create a small stack frame
397 mov a1, a2
424 s32i a2, a1, PT_SAR
425 s32i a3, a1, PT_PC
432 s32i a3, a1, PT_LBEG
435 s32i a3, a1, PT_LEND
452 s32i a3, a1, PT_PS
460 l32i a3, a1, PT_PS
481 l32i a2, a1, PT_SAR
[all …]
/u-boot/arch/m68k/cpu/mcf52x2/
A Dstart.S143 cmp.l %a0, %a1
206 jsr (%a1)
215 jsr (%a1)
219 jsr (%a1)
224 jsr (%a1)
255 cmp.l %a1,%a2
264 jmp (%a1)
277 clr.l (%a1)+
278 cmp.l %a1,%d1
296 cmp.l %a2, %a1
[all …]
/u-boot/arch/arm/lib/
A Dsetjmp.S18 stm a1, {v1-v8, ip, lr}
19 mov a1, #0
26 ldm a1, {v1-v8, ip, lr}
28 mov a1, a2
30 cmp a1, #0
32 mov a1, #1
/u-boot/arch/mips/mach-ath79/qca956x/
A Dqca956x-ddr-tap.S23 sw a1, 0x10(a0) /* Place where the First pass tap value is stored */
27 lw a1, 0x1c(a0) /* Reading the RST_RESET_ADDRESS */
29 or a1, a1, a2
30 sw a1, 0x1c(a0)
34 and a1, a1, a2
35 sw a1, 0x1c(a0) /* Taking the RTC out of RESET */
39 li a1, 0x1
40 sw a1, 0x0040(a0) /* RTC_SYNC_RESET_ADDRESS */
45 lw a1, 0x0044(a0) /* RTC_SYNC_STATUS_ADDRESS */
46 and a1, a2, a1
[all …]
/u-boot/arch/mips/mach-mtmips/mt7628/
A Dlowlevel_init.S70 li a1, CONFIG_SYS_ICACHE_SIZE
76 bne a0, a1, 1b
81 li a1, CONFIG_SYS_DCACHE_SIZE
87 bne a0, a1, 2b
99 li a1, CACHE_STACK_SIZE /* D-Cache lock size */
111 sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
112 bnez a1, 3b
138 li a1, CACHE_STACK_SIZE /* D-Cache unlock size */
143 sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
144 bnez a1, 1b
/u-boot/cmd/
A Dsmccc.c20 unsigned long a1; in do_call() local
33 a1 = argc > 2 ? hextoul(argv[2], NULL) : 0; in do_call()
42 arm_smccc_smc(fid, a1, a2, a3, a4, a5, a6, a7, &res); in do_call()
44 arm_smccc_hvc(fid, a1, a2, a3, a4, a5, a6, a7, &res); in do_call()
46 printf("Res: 0x%lx 0x%lx 0x%lx 0x%lx\n", res.a0, res.a1, res.a2, res.a3); in do_call()
/u-boot/fs/zfs/
A Dzfs_fletcher.c40 uint64_t a0, b0, a1, b1; in fletcher_2_endian() local
42 for (a0 = b0 = a1 = b1 = 0; ip < ipend; ip += 2) { in fletcher_2_endian()
44 a1 += zfs_to_cpu64(ip[1], endian); in fletcher_2_endian()
46 b1 += a1; in fletcher_2_endian()
50 zcp->zc_word[1] = cpu_to_zfs64(a1, endian); in fletcher_2_endian()
/u-boot/include/linux/
A Darm-smccc.h68 unsigned long a1; member
93 bool (*is_supported)(void (*invoke_fn)(unsigned long a0, unsigned long a1, unsigned long a2,
114 asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1,
131 asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
/u-boot/post/lib_powerpc/
A Dcomplex.c23 extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n);
33 int a1 = 666; in cpu_post_test_complex_1() local
40 if (cpu_post_complex_1_asm(a1, a2, a3, a4, n) != n * result) in cpu_post_test_complex_1()
/u-boot/arch/mips/mach-mtmips/mt7621/spl/
A Dlaunch_ll.S126 move a1, zero
147 li a1, CONFIG_SYS_ICACHE_LINE_SIZE
161 cache_loop t0, t1, a1, INDEX_STORE_TAG_I
165 cache_loop t0, t1, a1, FILL
168 cache_loop t0, t1, a1, INDEX_STORE_TAG_I
217 ext a1, t0, MVPCONF0_PVPE_SHIFT, 4
218 beqz a1, _vpe1_init_done
245 slt t1, a1, a2
247 move t1, a1
276 slt t1, a1, a2
/u-boot/doc/board/advantech/
A Dindex.rst9 imx8qm-rom7720-a1.rst
10 imx8qm-dmsse20-a1.rst
/u-boot/board/advantech/imx8qm_rom7720_a1/
A DMAINTAINERS1 i.MX8QM ROM 7720 a1 BOARD
5 F: arch/arm/dts/imx8qm-rom7720-a1.dts
/u-boot/board/advantech/imx8qm_dmsse20_a1/
A DMAINTAINERS1 i.MX8QM ROM DMSSE20 a1 BOARD
5 F: arch/arm/dts/imx8qm-dmsse20-a1.dtb
/u-boot/arch/riscv/cpu/
A Dstart.S52 mv s1, a1
234 mv a1, s0
241 mv a1, a0
252 mv a1, zero
267 mv s3, a1 /* save addr of gd */
369 mv a1, s2
376 mv a1, a0
398 mv a1, s4 /* dest_addr */
420 sub sp, a1, t0
/u-boot/arch/mips/include/asm/
A Dregdef.h24 #define a1 $5 macro
67 #define a1 $5 macro
/u-boot/arch/mips/mach-octeon/
A Dlowlevel_init.S71 ld a1, 8(t0)
75 sd a1, 8(t1)
126 ld a1, 0x10(t9)

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