| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| A D | qe_io.c | 30 int open_drain, int assign) in qe_cfg_iopin() argument
72 dbit_asgn = (u32)(assign << offset); in qe_cfg_iopin()
97 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) in qe_config_iopin() argument
102 qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign); in qe_config_iopin()
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| A D | cpu_init.c | 34 int open_drain, int assign);
40 int dir, open_drain, assign; in config_qe_ioports() local
43 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { in config_qe_ioports()
48 assign = qe_iop_conf_tab[i].assign; in config_qe_ioports()
49 qe_config_iopin(port, pin, dir, open_drain, assign); in config_qe_ioports()
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| /u-boot/drivers/pinctrl/ |
| A D | pinctrl-qe-io.c | 48 int open_drain, int assign) in qe_cfg_iopin() argument
90 dbit_asgn = (u32)(assign << offset); in qe_cfg_iopin()
115 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) in qe_config_iopin() argument
120 qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign); in qe_config_iopin()
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| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| A D | qe_io.c | 16 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) in qe_config_iopin() argument
58 pin_2bit_assign = (u32)(assign in qe_config_iopin()
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| A D | cpu_init.c | 136 int open_drain, int assign);
143 int dir, open_drain, assign; in config_qe_ioports() local
146 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { in config_qe_ioports()
151 assign = qe_iop_conf_tab[i].assign; in config_qe_ioports()
152 qe_config_iopin(port, pin, dir, open_drain, assign); in config_qe_ioports()
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| /u-boot/include/ |
| A D | ioports.h | 59 int assign; member
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| A D | fsl_qe.h | 276 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
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| /u-boot/doc/device-tree-bindings/gpio/ |
| A D | intel,x86-pinctrl.txt | 16 - mode-func - (optional) function number to assign to the pin. If
22 - pull-assign - (optional) this set the pull assignement (up/down) of the pin
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| /u-boot/doc/device-tree-bindings/mailbox/ |
| A D | mailbox.txt | 4 assign appropriate mailbox channel to client drivers.
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| /u-boot/doc/board/xilinx/ |
| A D | zynq.rst | 49 at runtime and assign the modeboot variable to specific bootmode string which
60 "modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot"
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| /u-boot/arch/arm/dts/ |
| A D | imx6ul-kontron-bl-common-u-boot.dtsi | 30 * in Linux we can't assign the shared reset GPIO to the PHYs, as this
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| A D | armada-388-clearfog.dts | 278 * PCIe uses ARP to assign addresses, or
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| /u-boot/doc/develop/ |
| A D | security.rst | 21 The U-Boot project cannot directly assign CVEs, nor do we require them for
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| /u-boot/doc/ |
| A D | README.atmel_mci | 16 The generic driver does NOT assign port pins to the MCI block
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| A D | README.console | 22 devices and their flags. You can assign a standard file (stdin,
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| A D | README.power-framework | 108 -- *battery_init - assign proper callbacks to be used by top
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| A D | README.usb | 217 have an assigned MAC address. In this case it is up to you to assign
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| A D | README.odroid | 189 then the below will automatically assign an ip address through DHCP.
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| /u-boot/arch/x86/dts/ |
| A D | baytrail_som-db5800-som-6867.dts | 48 pull-assign = <1>;
61 pull-assign = <1>;
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| A D | chromebook_coral.dts | 809 * If the Board has PERST_0 signal, assign the GPIO
810 * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
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| /u-boot/doc/usage/os/ |
| A D | vxworks.rst | 99 corresponding physical address and assign its value to "vx_phys_mem_base".
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| /u-boot/arch/arm/mach-imx/ |
| A D | Kconfig | 28 i.MX Resource domain controller is used to assign masters
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| /u-boot/common/ |
| A D | cli_hush.c | 2768 int assign = 0; local
2782 assign = 1;
2796 if (assign) {
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| /u-boot/doc/device-tree-bindings/pinctrl/ |
| A D | pinctrl-bindings.txt | 70 pinctrl-names: The list of names to assign states. List entry 0 defines the
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| /u-boot/scripts/ |
| A D | spelling.txt | 162 asign||assign
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