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Searched refs:base (Results 1 – 25 of 1265) sorted by relevance

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/u-boot/drivers/clk/imx/
A Dclk-imx8mp.c190 void __iomem *base; in imx8mp_clk_probe() local
193 base = (void *)ANATOP_BASE_ADDR; in imx8mp_clk_probe()
201 clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, in imx8mp_clk_probe()
203 clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, in imx8mp_clk_probe()
205 clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, in imx8mp_clk_probe()
207 clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, in imx8mp_clk_probe()
209 clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, in imx8mp_clk_probe()
254 base = dev_read_addr_ptr(dev); in imx8mp_clk_probe()
255 if (!base) in imx8mp_clk_probe()
275 clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480)); in imx8mp_clk_probe()
[all …]
A Dclk-imx8mq.c148 void __iomem *base; in imx8mq_clk_probe() local
244 base + 0x60, 13)); in imx8mq_clk_probe()
256 base + 0x0, 11)); in imx8mq_clk_probe()
259 base + 0x8, 11)); in imx8mq_clk_probe()
347 if (!base) { in imx8mq_clk_probe()
372 base + 0x8880)); in imx8mq_clk_probe()
392 base + 0xac00)); in imx8mq_clk_probe()
395 base + 0xac80)); in imx8mq_clk_probe()
474 base + 0xa980)); in imx8mq_clk_probe()
477 base + 0xaa00)); in imx8mq_clk_probe()
[all …]
A Dclk-imx8mm.c113 void __iomem *base; in imx8mm_clk_probe() local
179 base + 0x50, 13)); in imx8mm_clk_probe()
182 base + 0x84, 11)); in imx8mm_clk_probe()
233 if (!base) in imx8mm_clk_probe()
261 base + 0xac00)); in imx8mm_clk_probe()
264 base + 0xac80)); in imx8mm_clk_probe()
277 base + 0xbc80)); in imx8mm_clk_probe()
311 base + 0x8880)); in imx8mm_clk_probe()
314 base + 0xa980)); in imx8mm_clk_probe()
317 base + 0xaa00)); in imx8mm_clk_probe()
[all …]
A Dclk-imx8mn.c109 void __iomem *base; in imx8mn_clk_probe() local
175 base + 0x50, 13)); in imx8mn_clk_probe()
178 base + 0x84, 11)); in imx8mn_clk_probe()
229 if (!base) in imx8mn_clk_probe()
249 base + 0x8880)); in imx8mn_clk_probe()
260 base + 0xac00)); in imx8mn_clk_probe()
263 base + 0xac80)); in imx8mn_clk_probe()
276 base + 0xbc80)); in imx8mn_clk_probe()
323 base + 0xa980)); in imx8mn_clk_probe()
326 base + 0xaa00)); in imx8mn_clk_probe()
[all …]
A Dclk-imx6q.c42 void *base; in imx6q_clk_probe() local
45 base = (void *)ANATOP_BASE_ADDR; in imx6q_clk_probe()
49 base + 0x30, 0x1)); in imx6q_clk_probe()
52 base + 0x10, 0x3)); in imx6q_clk_probe()
65 base = dev_read_addr_ptr(dev); in imx6q_clk_probe()
66 if (!base) in imx6q_clk_probe()
84 base + 0x24, 11, 3)); in imx6q_clk_probe()
87 base + 0x24, 16, 3)); in imx6q_clk_probe()
90 base + 0x24, 19, 3)); in imx6q_clk_probe()
119 imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, in imx6q_clk_probe()
[all …]
A Dclk-imxrt1050.c34 void *base; in imxrt1050_clk_probe() local
54 base + 0x0, 0x7f)); in imxrt1050_clk_probe()
57 base + 0x30, 0x1)); in imxrt1050_clk_probe()
61 base + 0x10, 0x1)); in imxrt1050_clk_probe()
64 base + 0xa0, 0x7f)); in imxrt1050_clk_probe()
90 base + 0xa0, 19, 2)); in imxrt1050_clk_probe()
112 base = dev_read_addr_ptr(dev); in imxrt1050_clk_probe()
118 base + 0x10, 0, 3)); in imxrt1050_clk_probe()
147 base + 0x14, 10, 3)); in imxrt1050_clk_probe()
150 base + 0x24, 11, 3)); in imxrt1050_clk_probe()
[all …]
A Dclk-imxrt1020.c36 void *base; in imxrt1020_clk_probe() local
43 base + 0x30, 0x1)); in imxrt1020_clk_probe()
46 base + 0x10, 0x1)); in imxrt1020_clk_probe()
77 base = dev_read_addr_ptr(dev); in imxrt1020_clk_probe()
78 if (base == (void *)FDT_ADDR_T_NONE) in imxrt1020_clk_probe()
100 imx_clk_mux("semc_sel", base + 0x14, 6, 1, in imxrt1020_clk_probe()
105 base + 0x14, 10, 3)); in imxrt1020_clk_probe()
108 base + 0x24, 11, 3)); in imxrt1020_clk_probe()
111 base + 0x24, 16, 3)); in imxrt1020_clk_probe()
114 base + 0x24, 0, 6)); in imxrt1020_clk_probe()
[all …]
/u-boot/arch/arm/mach-keystone/
A Dddr3.c115 int ddr3_ecc_support_rmw(u32 base) in ddr3_ecc_support_rmw() argument
251 ddr3_ecc_config(base, ecc_val); in ddr3_ecc_init_range()
271 ddr3_ecc_config(base, ecc_val); in ddr3_enable_ecc()
274 void ddr3_disable_ecc(u32 base) in ddr3_disable_ecc() argument
276 ddr3_ecc_config(base, 0); in ddr3_disable_ecc()
280 static void cic_init(u32 base) in cic_init() argument
307 cic_init(base); in ddr3_map_ecc_cic2_irq()
316 ddr3_disable_ecc(base); in ddr3_init_ecc()
320 ddr3_ecc_init_range(base); in ddr3_init_ecc()
327 ddr3_enable_ecc(base, 0); in ddr3_init_ecc()
[all …]
/u-boot/drivers/i2c/
A Dmv_i2c.c141 writel(readl(&base->icr) & ~ICR_START, &base->icr); in i2c_transfer()
142 writel(readl(&base->icr) & ~ICR_STOP, &base->icr); in i2c_transfer()
145 writel(readl(&base->icr) | ICR_START, &base->icr); in i2c_transfer()
147 writel(readl(&base->icr) | ICR_STOP, &base->icr); in i2c_transfer()
152 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr); in i2c_transfer()
153 writel(readl(&base->icr) | ICR_TB, &base->icr); in i2c_transfer()
160 writel(readl(&base->isr) | ISR_ITE, &base->isr); in i2c_transfer()
176 writel(readl(&base->icr) & ~ICR_STOP, &base->icr); in i2c_transfer()
180 writel(readl(&base->icr) | ICR_STOP, &base->icr); in i2c_transfer()
186 writel(readl(&base->icr) | ICR_TB, &base->icr); in i2c_transfer()
[all …]
A Dintel_i2c.c61 u32 base; member
110 inb(base + SMBHSTCTL); in smbus_block_read()
118 (base + SMBHSTCTL)); in smbus_block_read()
120 outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT); in smbus_block_read()
123 outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL); in smbus_block_read()
180 outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT); in smbus_block_write()
190 outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL); in smbus_block_write()
251 ulong base; in intel_i2c_probe() local
256 base = priv->base; in intel_i2c_probe()
262 outb(inb(base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, base + SMBHSTCTL); in intel_i2c_probe()
[all …]
A Dsun8i_rsb.c31 stat = readl(&base->stat); in sun8i_rsb_await_trans()
67 writel(reg_addr, &base->addr); in sun8i_rsb_read()
70 ret = sun8i_rsb_do_trans(base); in sun8i_rsb_read()
83 writel(reg_addr, &base->addr); in sun8i_rsb_write()
84 writel(data, &base->data); in sun8i_rsb_write()
87 return sun8i_rsb_do_trans(base); in sun8i_rsb_write()
97 return sun8i_rsb_do_trans(base); in sun8i_rsb_set_device_address()
119 &base->dmcr); in sun8i_rsb_set_device_mode()
132 sun8i_rsb_set_clk(base); in sun8i_rsb_init()
182 return sun8i_rsb_init(base); in rsb_init()
[all …]
A Dsun6i_p2wi.c38 reg = readl(&base->status); in sun6i_p2wi_await_trans()
67 ret = sun6i_p2wi_await_trans(base); in sun6i_p2wi_read()
82 return sun6i_p2wi_await_trans(base); in sun6i_p2wi_write()
95 &base->pm); in sun6i_p2wi_change_to_p2wi_mode()
108 writel(P2WI_CTRL_RESET, &base->ctrl); in sun6i_p2wi_init()
111 &base->cc); in sun6i_p2wi_init()
147 sun6i_p2wi_init(base); in p2wi_init()
153 struct sunxi_p2wi_reg *base; member
162 return sun6i_p2wi_read(priv->base, in sun6i_p2wi_xfer()
166 return sun6i_p2wi_write(priv->base, in sun6i_p2wi_xfer()
[all …]
A Docteon_i2c.c183 void __iomem *base; member
377 twsi_stop(base); in twsi_start_unstick()
378 twsi_unblock(base); in twsi_start_unstick()
396 ret = twsi_wait(base); in twsi_start()
459 ret = twsi_wait(base); in twsi_write_data()
472 ret = twsi_wait(base); in twsi_write_data()
483 twsi_stop(base); in twsi_write_data()
557 ret = twsi_wait(base); in twsi_read_data()
569 ret = twsi_wait(base); in twsi_read_data()
579 twsi_stop(base); in twsi_read_data()
[all …]
A Dfsl_i2c.c247 writeb(0, &base->cr); in fsl_i2c_fixup()
253 readb(&base->dr); in fsl_i2c_fixup()
264 writeb(0, &base->sr); in fsl_i2c_fixup()
289 if (fsl_i2c_fixup(base)) in __i2c_init()
317 csr = readb(&base->sr); in i2c_wait()
321 csr = readb(&base->sr); in i2c_wait()
323 writeb(0x0, &base->sr); in i2c_wait()
352 &base->cr); in i2c_write_addr()
384 &base->cr); in __i2c_read_data()
387 readb(&base->dr); in __i2c_read_data()
[all …]
/u-boot/drivers/bios_emulator/
A Dbiosemui.h67 #define readb_le(base) *((u8*)(base)) argument
68 #define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) argument
69 #define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ argument
71 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
72 #define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
79 #define readb_le(base) *((u8*)(base)) argument
80 #define readw_le(base) *((u16*)(base)) argument
81 #define readl_le(base) *((u32*)(base)) argument
82 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
83 #define writew_le(base, v) *((u16*)(base)) = (v) argument
[all …]
/u-boot/arch/arm/mach-snapdragon/
A Dclock-qcs404.c132 clk_enable_gpll0(priv->base, &gpll0_vote_clk); in msm_set_rate()
133 clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); in msm_set_rate()
136 clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); in msm_set_rate()
165 clk_enable_cbc(priv->base + USB30_MASTER_CBCR); in msm_enable()
170 clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR); in msm_enable()
173 clk_enable_cbc(priv->base + USB30_SLEEP_CBCR); in msm_enable()
186 clk_enable_cbc(priv->base + ETH_PTP_CBCR); in msm_enable()
187 clk_enable_gpll0(priv->base, &gpll1_vote_clk); in msm_enable()
193 clk_enable_cbc(priv->base + ETH_RGMII_CBCR); in msm_enable()
194 clk_enable_gpll0(priv->base, &gpll1_vote_clk); in msm_enable()
[all …]
/u-boot/arch/arm/mach-uniphier/clk/
A Dpll-base-ld20.c39 tmp = readl(base); /* SSCPLLCTRL */ in uniphier_ld20_sscpll_init()
44 writel(tmp, base); in uniphier_ld20_sscpll_init()
46 tmp = readl(base + 4); in uniphier_ld20_sscpll_init()
51 writel(tmp, base + 4); in uniphier_ld20_sscpll_init()
58 writel(tmp, base + 4); in uniphier_ld20_sscpll_init()
70 writel(tmp, base); in uniphier_ld20_sscpll_ssc_en()
83 writel(tmp, base + 8); in uniphier_ld20_sscpll_set_regi()
95 writel(tmp, base); in uniphier_ld20_vpll27_init()
99 writel(tmp, base + 8); in uniphier_ld20_vpll27_init()
103 writel(tmp, base); in uniphier_ld20_vpll27_init()
[all …]
/u-boot/drivers/clk/at91/
A Dclk-sam9x60-pll.c41 void __iomem *base; member
98 void __iomem *base = pll->base; in sam9x60_frac_pll_set_rate() local
124 pmc_write(base, AT91_PMC_PLL_CTRL1, in sam9x60_frac_pll_set_rate()
143 void __iomem *base = pll->base; in sam9x60_frac_pll_get_rate() local
162 void __iomem *base = pll->base; in sam9x60_frac_pll_enable() local
227 void __iomem *base = pll->base; in sam9x60_frac_pll_disable() local
257 void __iomem *base = pll->base; in sam9x60_div_pll_enable() local
287 void __iomem *base = pll->base; in sam9x60_div_pll_disable() local
305 void __iomem *base = pll->base; in sam9x60_div_pll_set_rate() local
346 void __iomem *base = pll->base; in sam9x60_div_pll_get_rate() local
[all …]
/u-boot/drivers/virtio/
A Dvirtio_mmio.c26 void __iomem *base = priv->base + VIRTIO_MMIO_CONFIG; in virtio_mmio_get_config() local
36 ptr[i] = readb(base + offset + i); in virtio_mmio_get_config()
43 b = readb(base + offset); in virtio_mmio_get_config()
47 w = cpu_to_le16(readw(base + offset)); in virtio_mmio_get_config()
51 l = cpu_to_le32(readl(base + offset)); in virtio_mmio_get_config()
55 l = cpu_to_le32(readl(base + offset)); in virtio_mmio_get_config()
71 void __iomem *base = priv->base + VIRTIO_MMIO_CONFIG; in virtio_mmio_set_config() local
81 writeb(ptr[i], base + offset + i); in virtio_mmio_set_config()
89 writeb(b, base + offset); in virtio_mmio_set_config()
93 writew(le16_to_cpu(w), base + offset); in virtio_mmio_set_config()
[all …]
/u-boot/drivers/serial/
A Dserial_mvebu_a3700.c16 void __iomem *base; member
41 void __iomem *base = plat->base; in mvebu_serial_putc() local
46 writel(ch, base + UART_TX_REG); in mvebu_serial_putc()
54 void __iomem *base = plat->base; in mvebu_serial_getc() local
65 void __iomem *base = plat->base; in mvebu_serial_pending() local
81 void __iomem *base = plat->base; in mvebu_serial_setbrg() local
153 void __iomem *base = plat->base; in mvebu_serial_probe() local
201 base + UART_CTRL_REG); in mvebu_serial_probe()
204 writel(0, base + UART_CTRL_REG); in mvebu_serial_probe()
212 void __iomem *base = plat->base; in mvebu_serial_remove() local
[all …]
A Dserial_bcm6345.c86 void __iomem *base; member
112 readl(base + UART_FIFO_REG); in bcm6345_serial_flush()
120 bcm6345_serial_disable(base); in bcm6345_serial_init()
121 bcm6345_serial_flush(base); in bcm6345_serial_init()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
168 writel(0, base + UART_IR_REG); in bcm6345_serial_init()
171 bcm6345_serial_enable(base); in bcm6345_serial_init()
233 priv->base = dev_remap_addr(dev); in bcm6345_serial_probe()
234 if (!priv->base) in bcm6345_serial_probe()
290 wait_xfered(base); in _debug_uart_putc()
[all …]
/u-boot/drivers/pch/
A Dpch9.c27 u32 base; in pch9_get_gpio_base() local
39 dm_pci_read_config32(dev, GPIO_BASE, &base); in pch9_get_gpio_base()
40 if (base == 0x00000000 || base == 0xffffffff) { in pch9_get_gpio_base()
51 *gbasep = base & 1 ? base & ~3 : base & ~15; in pch9_get_gpio_base()
58 u32 base; in pch9_get_io_base() local
60 dm_pci_read_config32(dev, IO_BASE, &base); in pch9_get_io_base()
61 if (base == 0x00000000 || base == 0xffffffff) { in pch9_get_io_base()
66 *iobasep = base & 1 ? base & ~3 : base & ~15; in pch9_get_io_base()
/u-boot/board/intel/galileo/
A Dgalileo.c23 u32 base, port, val; in board_assert_perst() local
26 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); in board_assert_perst()
27 base = (base & 0xffff) & ~0x7f; in board_assert_perst()
30 port = base + 0x20; in board_assert_perst()
36 port = base + 0x24; in board_assert_perst()
42 port = base + 0x28; in board_assert_perst()
50 u32 base, port, val; in board_deassert_perst() local
53 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); in board_deassert_perst()
54 base = (base & 0xffff) & ~0x7f; in board_deassert_perst()
57 port = base + 0x28; in board_deassert_perst()
/u-boot/drivers/soc/ti/
A Dkeystone_serdes.c158 base + SERDES_PLL_CTL_REG); in ks2_serdes_pll_enable()
164 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), in ks2_serdes_lane_reset()
167 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), in ks2_serdes_lane_reset()
171 static void ks2_serdes_lane_enable(u32 base, in ks2_serdes_lane_enable() argument
175 ks2_serdes_lane_reset(base, 0, lane); in ks2_serdes_lane_enable()
179 base + SERDES_LANE_CTL_STATUS_REG(lane)); in ks2_serdes_lane_enable()
183 ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane), in ks2_serdes_lane_enable()
201 ks2_serdes_init_cfg(base, &cfgs[i], num_lanes); in ks2_serdes_init()
203 ks2_serdes_cmu_comlane_enable(base, serdes); in ks2_serdes_init()
205 ks2_serdes_lane_enable(base, serdes, i); in ks2_serdes_init()
[all …]
/u-boot/drivers/misc/
A Dk3_esm.c65 value = readl(base + ESM_STS(pin)); in esm_clear_raw_status()
68 writel(value, base + ESM_STS(pin)); in esm_clear_raw_status()
78 void __iomem *base; in k3_esm_probe() local
83 base = dev_remap_addr_index(dev, 0); in k3_esm_probe()
84 if (!base) in k3_esm_probe()
108 writel(ESM_SFT_RST_KEY, base + ESM_SFT_RST); in k3_esm_probe()
111 esm_intr_prio_set(base, pins[i]); in k3_esm_probe()
112 esm_clear_raw_status(base, pins[i]); in k3_esm_probe()
113 esm_pin_enable(base, pins[i]); in k3_esm_probe()
114 esm_intr_enable(base, pins[i]); in k3_esm_probe()
[all …]

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12345678910>>...51