Home
last modified time | relevance | path

Searched refs:c0 (Results 1 – 25 of 97) sorted by relevance

1234

/u-boot/arch/arm/mach-rmobile/
A Dlowlevel_init_ca15.S15 mrc p15, 0, r4, c0, c0, 5 /* mpidr */
48 mrceq p15, 0, r0, c1, c0, 1 /* actlr */
50 mcreq p15, 0, r0, c1, c0, 1
53 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
59 mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
67 mcrne p15, 1, r0, c9, c0, 2
73 mrc p15, 0, r0, c1, c0, 1
75 mcr p15, 0, r0, c1, c0, 1
/u-boot/arch/arm/cpu/armv7/
A Dstart.S83 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
106 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
113 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
197 mrc p15, 0, r0, c1, c0, 0
207 mcr p15, 0, r0, c1, c0, 0
245 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
281 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
306 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
317 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
331 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
[all …]
A Dcache_v7_asm.S27 mrc p15, 1, r0, c0, c0, 1 @ read clidr
39 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
41 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
69 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
98 mrc p15, 1, r0, c0, c0, 1 @ read clidr
109 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
111 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
139 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
A Dnonsec_virt.S32 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
48 mcr p15, 0, r5, c12, c0, 1
61 mrc p15, 0, r5, c1, c0, 1
63 mcr p15, 0, r5, c1, c0, 1
68 mrc p15, 0, r5, c1, c0, 1
70 mcr p15, 0, r5, c1, c0, 1
93 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
118 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
193 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
197 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
[all …]
A Dpsci.S163 mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
172 mrc p15, 1, r0, c0, c0, 1 @ read clidr
184 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
186 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
211 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
219 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
221 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
228 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
230 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
242 mrc p15, 0, r0, c1, c0, 0 @ SCTLR
[all …]
A Dsctlr.S18 mrc p15, 0, r0, c1, c0, 0 @ load system control register
20 mcr p15, 0, r0, c1, c0, 0 @ write system control register
/u-boot/board/freescale/t104xrdb/
A Dt104x_pbi_sb.cfg10 091380c0 000f0000
15 091380c0 00000100
36 091380c0 000FFFFF
38 091380c0 000FFFFF
A Dt104x_pbi.cfg10 091380c0 000f0000
15 091380c0 00000100
36 091380c0 000FFFFF
/u-boot/arch/arm/mach-uniphier/arm32/
A Dlowlevel_init.S23 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
25 mcr p15, 0, r0, c1, c0, 0
42 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
44 mcr p15, 0, r0, c1, c0, 0
53 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
56 mcr p15, 0, r0, c2, c0, 2
59 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
65 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
74 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
76 mcr p15, 0, r0, c1, c0, 0
A Dpsci_smp.S14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
17 mcr p15, 0, r1, c1, c0, 0
26 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
/u-boot/arch/arm/mach-imx/mx7/
A Dpsci-suspend.S19 mcr p15, 2, r0, c0, c0, 0
20 mrc p15, 1, r0, c0, c0, 0
61 mcr p15, 0, r6, c1, c0, 0
/u-boot/arch/arm/cpu/armv7/sunxi/
A Dfel_utils.S19 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
21 mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
31 mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
33 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
/u-boot/arch/arm/mach-mediatek/mt7629/
A Dlowlevel_init.S29 mcr p15, 0, r0, c14, c0, 0
44 mrc p15, 0, r0, c1, c0, 1
46 mcr p15, 0, r0, c1, c0, 1
49 mrc p15, 0, r0, c0, c0, 5
/u-boot/arch/arm/mach-mvebu/
A Dlowlevel.S30 mrc p15, 0, r0, c1, c0, 0
32 mcr p15, 0, r0, c1, c0, 0
52 mcr p15, 4, r0, c15, c0
/u-boot/arch/arm/mach-k3/
A Dlowlevel_init.S11 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
/u-boot/arch/arm/dts/
A Dstih407-clock.dtsi98 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
105 clock-output-names = "clk-s-c0-fs0-ch0",
106 "clk-s-c0-fs0-ch1",
107 "clk-s-c0-fs0-ch2",
108 "clk-s-c0-fs0-ch3";
109 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
116 clk_s_c0_pll0: clk-s-c0-pll0 {
122 clock-output-names = "clk-s-c0-pll0-odf-0";
126 clk_s_c0_pll1: clk-s-c0-pll1 {
132 clock-output-names = "clk-s-c0-pll1-odf-0";
[all …]
A Dstih410-clock.dtsi99 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
106 clock-output-names = "clk-s-c0-fs0-ch0",
107 "clk-s-c0-fs0-ch1",
108 "clk-s-c0-fs0-ch2",
109 "clk-s-c0-fs0-ch3";
110 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
117 clk_s_c0_pll0: clk-s-c0-pll0 {
123 clock-output-names = "clk-s-c0-pll0-odf-0";
127 clk_s_c0_pll1: clk-s-c0-pll1 {
133 clock-output-names = "clk-s-c0-pll1-odf-0";
[all …]
/u-boot/arch/arm/mach-zynq/
A Dlowlevel_init.S13 mrc p15, 0, r1, c1, c0, 2
16 mcr p15, 0, r1, c1, c0, 2
/u-boot/arch/arm/mach-mediatek/mt7623/
A Dlowlevel_init.S18 mrc p15, 0, r0, c1, c0, 1
20 mcr p15, 0, r0, c1, c0, 1
/u-boot/board/freescale/t102xrdb/
A Dt1024_pbi.cfg5 091380c0 00000100
26 091380c0 000FFFFF
/u-boot/board/freescale/t4rdb/
A Dt4_pbi.cfg11 091380c0 00000100
27 091380c0 00100000
/u-boot/arch/arm/cpu/arm11/
A Dsctlr.S20 mrc p15, 0, r0, c1, c0, 0 @ load system control register
23 mcr p15, 0, r0, c1, c0, 0 @ write system control register
/u-boot/arch/arm/mach-aspeed/ast2600/
A Dlowlevel_init.S93 mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ
112 mrc p15, 0, r0, c1, c0, 1
114 mcr p15, 0, r0, c1, c0, 1
120 mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register
/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dstart.S64 mrc p15, 0, r2, c1, c0, 0
85 mcr p15, 0, r2, c1, c0, 0
/u-boot/arch/arm/cpu/arm926ejs/sunxi/
A Dfel_utils.S19 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
29 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR register

Completed in 41 milliseconds

1234