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/u-boot/arch/arm/dts/
A Dk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
94 compatible = "cache";
95 cache-level = <2>;
98 cache-sets = <512>;
103 compatible = "cache";
104 cache-level = <2>;
107 cache-sets = <512>;
[all …]
A Dk3-am62a7.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
60 i-cache-sets = <256>;
63 d-cache-sets = <128>;
74 i-cache-sets = <256>;
77 d-cache-sets = <128>;
88 i-cache-sets = <256>;
91 d-cache-sets = <128>;
97 compatible = "cache";
98 cache-level = <2>;
[all …]
A Dk3-am625.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
60 i-cache-sets = <256>;
63 d-cache-sets = <128>;
74 i-cache-sets = <256>;
77 d-cache-sets = <128>;
88 i-cache-sets = <256>;
91 d-cache-sets = <128>;
97 compatible = "cache";
98 cache-level = <2>;
[all …]
A Dk3-am642.dtsi34 i-cache-size = <0x8000>;
36 i-cache-sets = <256>;
37 d-cache-size = <0x8000>;
39 d-cache-sets = <128>;
50 i-cache-sets = <256>;
53 d-cache-sets = <128>;
59 compatible = "cache";
60 cache-level = <2>;
61 cache-size = <0x40000>;
62 cache-line-size = <64>;
[all …]
A Dsynquacer-sc2a11-caches.dtsi9 i-cache-size = <0x8000>; \
10 i-cache-line-size = <64>; \
11 i-cache-sets = <256>; \
12 d-cache-size = <0x8000>; \
13 d-cache-line-size = <64>; \
41 L3: l3-cache {
42 cache-level = <3>;
43 cache-size = <0x400000>;
44 cache-line-size = <64>;
45 cache-sets = <4096>;
[all …]
A Djuno-r2.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
113 i-cache-sets = <256>;
116 d-cache-sets = <256>;
131 i-cache-sets = <256>;
134 d-cache-sets = <128>;
149 i-cache-sets = <256>;
152 d-cache-sets = <128>;
167 i-cache-sets = <256>;
200 cache-sets = <2048>;
[all …]
A Dk3-j7200.dtsi60 i-cache-sets = <256>;
63 d-cache-sets = <128>;
74 i-cache-sets = <256>;
77 d-cache-sets = <128>;
83 compatible = "cache";
84 cache-level = <2>;
85 cache-size = <0x100000>;
86 cache-line-size = <64>;
87 cache-sets = <2048>;
92 compatible = "cache";
[all …]
A Dk3-j721s2.dtsi46 i-cache-size = <0xc000>;
48 i-cache-sets = <256>;
51 d-cache-sets = <256>;
62 i-cache-sets = <256>;
65 d-cache-sets = <256>;
71 compatible = "cache";
72 cache-level = <2>;
74 cache-line-size = <64>;
75 cache-sets = <1024>;
80 compatible = "cache";
[all …]
A Dvf610.dtsi8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 {
13 compatible = "arm,pl310-cache";
15 cache-unified;
16 cache-level = <2>;
A Dk3-j721e.dtsi61 i-cache-sets = <256>;
64 d-cache-sets = <128>;
75 i-cache-sets = <256>;
78 d-cache-sets = <128>;
84 compatible = "cache";
85 cache-level = <2>;
86 cache-size = <0x100000>;
87 cache-line-size = <64>;
88 cache-sets = <2048>;
93 compatible = "cache";
[all …]
/u-boot/arch/x86/lib/
A Dmrccache.c45 return cache && (cache->signature == MRC_DATA_SIGNATURE); in is_mrc_cache()
56 cache = NULL; in mrccache_find_current()
62 cache = next; in mrccache_find_current()
74 if (cache->checksum != compute_ip_checksum(cache->data, in mrccache_find_current()
82 return cache; in mrccache_find_current()
121 return cache; in find_next_mrc_cache()
153 if (cache && (cache->data_size == cur->data_size) && in mrccache_update()
160 if (cache) in mrccache_update()
204 memcpy(cache->data, mrc->buf, cache->data_size); in mrccache_setup()
206 mrc->cache = cache; in mrccache_setup()
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/u-boot/fs/ext4/
A Dext4fs.c72 ext_cache_init(&cache); in ext4fs_read_file()
79 ext_cache_fini(&cache); in ext4fs_read_file()
182 ext_cache_fini(&cache); in ext4fs_read_file()
279 memset(cache, 0, sizeof(*cache)); in ext_cache_init()
284 free(cache->buf); in ext_cache_fini()
285 ext_cache_init(cache); in ext_cache_fini()
291 if (cache->buf && cache->block == block && cache->size == size) in ext_cache_read()
293 ext_cache_fini(cache); in ext_cache_read()
295 if (!cache->buf) in ext_cache_read()
301 cache->block = block; in ext_cache_read()
[all …]
/u-boot/doc/device-tree-bindings/arm/
A Dl2c2x0.txt15 "arm,pl310-cache"
16 "arm,l220-cache"
17 "arm,l210-cache"
21 cache controller
28 "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
30 - cache-unified : Specifies the cache is a unified cache.
31 - cache-level : Should be set to 2 for a level 2 cache.
52 - cache-size : specifies the size in bytes of the cache
54 - cache-block-size : specifies the size in bytes of a cache block
57 cache block size
[all …]
/u-boot/drivers/cache/
A DKconfig11 Enable driver model for cache controllers that are found on
17 tristate "PL310 cache driver"
21 This driver is for the PL310 cache controller commonly found on
22 ARMv7(32-bit) devices. The driver configures the cache settings
26 bool "Andes V5L2 cache driver"
29 Support Andes V5L2 cache controller in AE350 platform.
31 device tree and enable L2 cache.
34 bool "Arteris Ncore cache coherent unit driver"
42 bool "SiFive composable cache"
45 This driver is for SiFive Composable L2/L3 cache. It enables cache
[all …]
A DMakefile2 obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o
4 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
5 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
6 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
7 obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
/u-boot/doc/
A DREADME.arm-caches1 Disabling I-cache:
4 Disabling D-cache:
7 Enabling I-cache:
10 Enabling D-cache:
15 D-cache from this function. This function is called immediately
18 Guidelines for Working with D-cache:
26 lines from the DMA buffer in the cache, subsequent cache-line replacements
29 into the cache while the DMA is going on.
47 - cleanup_before_linux() should flush the D-cache, invalidate I-cache, and
50 1. dcache_disable() - flushes and disables d-cache
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/u-boot/arch/powerpc/dts/
A Dt104xsi-pre.dtsi51 next-level-cache = <&L2_1>;
53 L2_1: l2-cache {
54 next-level-cache = <&cpc>;
61 next-level-cache = <&L2_2>;
63 L2_2: l2-cache {
64 next-level-cache = <&cpc>;
71 next-level-cache = <&L2_3>;
73 L2_3: l2-cache {
74 next-level-cache = <&cpc>;
81 next-level-cache = <&L2_4>;
[all …]
/u-boot/arch/riscv/dts/
A Dfu540-c000.dtsi29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
43 d-cache-sets = <64>;
49 i-cache-sets = <64>;
67 d-cache-sets = <64>;
73 i-cache-sets = <64>;
91 d-cache-sets = <64>;
97 i-cache-sets = <64>;
115 d-cache-sets = <64>;
263 cache-level = <2>;
[all …]
A Dfu740-c000.dtsi29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
44 d-cache-sets = <64>;
45 d-cache-size = <32768>;
50 i-cache-sets = <128>;
68 d-cache-sets = <64>;
74 i-cache-sets = <128>;
92 d-cache-sets = <64>;
116 d-cache-sets = <64>;
271 cache-level = <2>;
[all …]
A Dae350_32.dts38 i-cache-size = <0x8000>;
39 i-cache-line-size = <32>;
40 d-cache-size = <0x8000>;
41 d-cache-line-size = <32>;
42 next-level-cache = <&L2>;
59 i-cache-size = <0x8000>;
61 d-cache-size = <0x8000>;
114 L2: l2-cache@e0500000 {
115 compatible = "cache";
116 cache-level = <2>;
[all …]
A Dae350_64.dts38 i-cache-size = <0x8000>;
39 i-cache-line-size = <32>;
40 d-cache-size = <0x8000>;
41 d-cache-line-size = <32>;
42 next-level-cache = <&L2>;
59 i-cache-size = <0x8000>;
61 d-cache-size = <0x8000>;
114 L2: l2-cache@e0500000 {
115 compatible = "cache";
116 cache-level = <2>;
[all …]
/u-boot/arch/x86/lib/fsp2/
A Dfsp_meminit.c25 struct mrc_data_container *cache; in prepare_mrc_cache_type() local
32 cache = mrccache_find_current(&entry); in prepare_mrc_cache_type()
33 if (!cache) in prepare_mrc_cache_type()
36 log_debug("MRC at %x, size %x\n", (uint)cache->data, cache->data_size); in prepare_mrc_cache_type()
37 *cachep = cache; in prepare_mrc_cache_type()
44 struct mrc_data_container *cache; in prepare_mrc_cache() local
47 ret = prepare_mrc_cache_type(MRC_TYPE_NORMAL, &cache); in prepare_mrc_cache()
50 upd->arch.nvs_buffer_ptr = cache->data; in prepare_mrc_cache()
52 ret = prepare_mrc_cache_type(MRC_TYPE_VAR, &cache); in prepare_mrc_cache()
55 upd->config.variable_nvs_buffer_ptr = cache->data; in prepare_mrc_cache()
/u-boot/arch/x86/lib/fsp1/
A Dfsp_common.c27 struct mrc_data_container *cache; in fsp_prepare_mrc_cache() local
35 cache = mrccache_find_current(&entry); in fsp_prepare_mrc_cache()
36 if (!cache) in fsp_prepare_mrc_cache()
40 cache->data, cache->data_size, cache->checksum); in fsp_prepare_mrc_cache()
42 return cache->data; in fsp_prepare_mrc_cache()
/u-boot/arch/arm/cpu/armv7/
A Dcache_v7_asm.S32 mov r10, #0 @ start clean at cache level 0
35 mov r1, r0, lsr r2 @ extract cache type bits from clidr
37 cmp r1, #2 @ see what cache we have at this level
38 blt skip @ skip if no cache, or just i-cache
64 add r10, r10, #2 @ increment cache number
68 mov r10, #0 @ swith back to cache level 0
102 mov r10, #0 @ start clean at cache level 0
107 cmp r1, #2 @ see what cache we have at this level
108 blt inval_skip @ skip if no cache, or just i-cache
134 add r10, r10, #2 @ increment cache number
[all …]
/u-boot/arch/x86/cpu/quark/
A Ddram.c26 struct mrc_data_container *cache; in prepare_mrc_cache() local
34 cache = mrccache_find_current(&entry); in prepare_mrc_cache()
35 if (!cache) in prepare_mrc_cache()
39 cache->data, cache->data_size, cache->checksum); in prepare_mrc_cache()
42 memcpy(&mrc_params->timings, cache->data, cache->data_size); in prepare_mrc_cache()
132 char *cache; in dram_init() local
158 cache = malloc(sizeof(struct mrc_timings)); in dram_init()
159 if (cache) { in dram_init()
162 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); in dram_init()
163 mrc->buf = cache; in dram_init()

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