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Searched refs:ccm (Results 1 – 25 of 99) sorted by relevance

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/u-boot/arch/arm/mach-sunxi/
A Dclock_sun9i.c23 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
42 &ccm->ahb0_cfg); in clock_init_safe()
45 &ccm->ahb1_cfg); in clock_init_safe()
48 &ccm->ahb2_cfg); in clock_init_safe()
51 &ccm->apb0_cfg); in clock_init_safe()
55 &ccm->gtbus_cfg); in clock_init_safe()
58 &ccm->cci400_cfg); in clock_init_safe()
75 setbits_le32(&ccm->apb1_gate, in clock_init_uart()
98 &ccm->pll1_c0_cfg); in clock_set_pll1()
124 &ccm->pll2_c1_cfg); in clock_set_pll2()
[all …]
A Dclock_sun8i_a83t.c22 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
28 writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); in clock_init_safe()
32 writel(0x0, &ccm->cci400_cfg); in clock_init_safe()
54 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
61 &ccm->apb2_div); in clock_init_uart()
64 setbits_le32(&ccm->apb2_gate, in clock_init_uart()
69 setbits_le32(&ccm->apb2_reset_cfg, in clock_init_uart()
86 &ccm->cpu_axi_cfg); in clock_set_pll1()
91 &ccm->pll1_c0_cfg); in clock_set_pll1()
96 &ccm->pll1_c1_cfg); in clock_set_pll1()
[all …]
A Dclock_sun6i.c23 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
97 setbits_le32(&ccm->apb1_gate, in clock_init_uart()
110 &ccm->apb2_div); in clock_init_uart()
113 setbits_le32(&ccm->apb2_gate, in clock_init_uart()
147 &ccm->cpu_axi_cfg); in clock_set_pll1()
152 &ccm->cpu_axi_cfg); in clock_set_pll1()
167 &ccm->cpu_axi_cfg); in clock_set_pll1()
172 &ccm->cpu_axi_cfg); in clock_set_pll1()
195 &ccm->pll3_cfg); in clock_set_pll3()
207 &ccm->pll3_cfg); in clock_set_pll3_factors()
[all …]
A Dclock_sun50i_h6.c10 struct sunxi_ccm_reg *const ccm = in clock_init_safe() local
54 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
61 &ccm->apb2_cfg); in clock_init_uart()
75 struct sunxi_ccm_reg * const ccm = in clock_set_pll1() local
83 val = readl(&ccm->cpu_axi_cfg); in clock_set_pll1()
86 writel(val, &ccm->cpu_axi_cfg); in clock_set_pll1()
97 val = readl(&ccm->cpu_axi_cfg); in clock_set_pll1()
100 writel(val, &ccm->cpu_axi_cfg); in clock_set_pll1()
106 struct sunxi_ccm_reg *const ccm = in clock_get_pll6() local
122 struct sunxi_ccm_reg *const ccm = in clock_twi_onoff() local
[all …]
A Dclock_sun4i.c20 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
28 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
35 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
49 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
56 &ccm->apb1_clk_div_cfg); in clock_init_uart()
59 setbits_le32(&ccm->apb1_gate, in clock_init_uart()
65 struct sunxi_ccm_reg *const ccm = in clock_twi_onoff() local
70 setbits_le32(&ccm->apb1_gate, in clock_twi_onoff()
73 clrbits_le32(&ccm->apb1_gate, in clock_twi_onoff()
157 &ccm->cpu_ahb_apb0_cfg); in clock_set_pll1()
[all …]
A Dclock.c42 struct sunxi_ccm_reg *const ccm = in clock_twi_onoff() local
57 setbits_le32(&ccm->apb2_gate, in clock_twi_onoff()
59 setbits_le32(&ccm->apb2_reset_cfg, in clock_twi_onoff()
62 clrbits_le32(&ccm->apb2_reset_cfg, in clock_twi_onoff()
64 clrbits_le32(&ccm->apb2_gate, in clock_twi_onoff()
/u-boot/board/tbs/tbs2910/
A Dtbs2910.c84 reg = readl(&ccm->analog_pll_video); in setup_display()
86 writel(reg, &ccm->analog_pll_video); in setup_display()
92 writel(reg, &ccm->analog_pll_video); in setup_display()
98 writel(reg, &ccm->analog_pll_video); in setup_display()
106 reg = readl(&ccm->analog_pll_video); in setup_display()
112 reg = readl(&ccm->CCGR3); in setup_display()
114 writel(reg, &ccm->CCGR3); in setup_display()
117 reg = readl(&ccm->chsccdr); in setup_display()
124 writel(reg, &ccm->chsccdr); in setup_display()
127 reg = readl(&ccm->CCGR3); in setup_display()
[all …]
/u-boot/board/toradex/colibri_vf/
A Dcolibri_vf.c224 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
229 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
231 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
235 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
237 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
240 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
242 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
244 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
246 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
277 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, in clock_init()
[all …]
/u-boot/arch/arm/cpu/armv7/vf610/
A Dgeneric.c34 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in enable_ocotp_clk() local
37 reg = readl(&ccm->ccgr6); in enable_ocotp_clk()
42 writel(reg, &ccm->ccgr6); in enable_ocotp_clk()
48 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_mcu_main_clk() local
53 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
57 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk()
115 ccm_cacrr = readl(&ccm->cacrr); in get_bus_clk()
129 ccm_cacrr = readl(&ccm->cacrr); in get_ipg_clk()
149 ccm_cscmr1 = readl(&ccm->cscmr1); in get_sdhc_clk()
153 ccm_cscdr2 = readl(&ccm->cscdr2); in get_sdhc_clk()
[all …]
/u-boot/board/bsh/imx6ulz_smm_m2/
A Dspl.c101 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
103 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
104 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
105 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
106 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
107 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
108 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
109 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
/u-boot/board/phytec/pcm052/
A Dpcm052.c222 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
224 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
226 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
231 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
233 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
236 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
238 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
240 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
250 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, in clock_init()
252 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, in clock_init()
[all …]
/u-boot/board/freescale/vf610twr/
A Dvf610twr.c275 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
277 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
279 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
284 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
286 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
289 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
291 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
293 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
303 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, in clock_init()
305 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, in clock_init()
[all …]
/u-boot/arch/arm/mach-imx/mx6/
A Dlitesom.c152 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
154 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
155 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
156 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
157 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
158 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
159 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
160 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
161 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
A Dopos6ul.c162 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
164 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
165 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
166 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
167 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
168 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
169 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
170 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
171 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/u-boot/arch/m68k/cpu/mcf5445x/
A Dspeed.c33 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_enter_limp() local
46 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
55 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_exit_limp() local
59 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
69 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5441x_clocks() local
73 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; in setup_5441x_clocks()
101 setbits_be16(&ccm->misccr2, 0x02); in setup_5441x_clocks()
114 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */ in setup_5441x_clocks()
/u-boot/board/sunxi/
A Dgmac.c9 struct sunxi_ccm_reg *const ccm = in eth_init_board() local
14 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | in eth_init_board()
16 setbits_le32(&ccm->gmac_clk_cfg, in eth_init_board()
19 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | in eth_init_board()
/u-boot/board/engicam/common/
A Dspl.c361 writel(0x00003F3F, &ccm->CCGR0); in ccgr_init()
362 writel(0x0030FC00, &ccm->CCGR1); in ccgr_init()
363 writel(0x000FC000, &ccm->CCGR2); in ccgr_init()
364 writel(0x3F300000, &ccm->CCGR3); in ccgr_init()
365 writel(0xFF00F300, &ccm->CCGR4); in ccgr_init()
366 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
367 writel(0x000003CC, &ccm->CCGR6); in ccgr_init()
369 writel(0x00c03f3f, &ccm->CCGR0); in ccgr_init()
370 writel(0xfcffff00, &ccm->CCGR1); in ccgr_init()
371 writel(0x0cffffcc, &ccm->CCGR2); in ccgr_init()
[all …]
/u-boot/board/bticino/mamoj/
A Dspl.c144 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
146 writel(0x00003f3f, &ccm->CCGR0); in ccgr_init()
147 writel(0x0030fc00, &ccm->CCGR1); in ccgr_init()
148 writel(0x000fc000, &ccm->CCGR2); in ccgr_init()
149 writel(0x3f300000, &ccm->CCGR3); in ccgr_init()
150 writel(0xff00f300, &ccm->CCGR4); in ccgr_init()
151 writel(0x0f0000c3, &ccm->CCGR5); in ccgr_init()
152 writel(0x000003cc, &ccm->CCGR6); in ccgr_init()
/u-boot/arch/m68k/cpu/mcf532x/
A Dspeed.c54 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in get_sys_clock() local
59 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { in get_sys_clock()
60 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
92 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_limp() local
102 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); in clock_limp()
105 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); in clock_limp()
107 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_limp()
115 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_exit_limp() local
119 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
122 while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK)) in clock_exit_limp()
/u-boot/board/variscite/dart_6ul/
A Dspl.c93 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
95 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
96 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
97 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
98 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
99 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
100 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
101 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
102 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/u-boot/board/technexion/pico-imx6ul/
A Dspl.c99 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
101 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
102 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
103 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
104 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
105 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
106 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
107 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
/u-boot/board/myir/mys_6ulx/
A Dspl.c87 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
89 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
90 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
91 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
92 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
93 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
94 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
95 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
/u-boot/board/phytec/pcl063/
A Dspl.c88 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
90 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
91 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
92 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
93 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
94 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
95 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
96 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
/u-boot/board/seeed/npi_imx6ull/
A Dspl.c86 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
88 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
89 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
90 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
91 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
92 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
93 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
94 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
/u-boot/board/k+p/kp_imx6q_tpc/
A Dkp_imx6q_tpc_spl.c26 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
28 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
29 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
30 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
31 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
32 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
33 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
34 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()

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