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Searched refs:chan (Results 1 – 25 of 68) sorted by relevance

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/u-boot/drivers/ddr/marvell/axp/
A Dxor.c146 val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) in mv_xor_ctrl_set()
172 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
175 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), tmp); in mv_xor_mem_init()
187 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
203 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
262 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_transfer()
304 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), tmp); in mv_xor_transfer()
310 reg_write(XOR_NEXT_DESC_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_transfer()
314 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_transfer()
405 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_cmd_set()
[all …]
A Dxor_regs.h13 #define XOR_UNIT(chan) ((chan) >> 1) argument
14 #define XOR_CHAN(chan) ((chan) & 1) argument
25 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4))) argument
26 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4))) argument
35 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4))) argument
36 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4))) argument
37 #define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x220 + ((chan) * 4))) argument
39 #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2B0 + ((chan) * 4))) argument
40 #define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2C0 + ((chan) * 4))) argument
100 #define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x240 + ((chan) * 4))) argument
/u-boot/drivers/pwm/
A Dsandbox_pwm.c44 chan = &priv->chan[channel]; in sandbox_pwm_get_config()
46 *duty_nsp = chan->duty_ns; in sandbox_pwm_get_config()
47 *enablep = chan->enable; in sandbox_pwm_get_config()
48 *polarityp = chan->polarity; in sandbox_pwm_get_config()
61 chan = &priv->chan[channel]; in sandbox_pwm_set_config()
65 chan->period_ns = 4096; in sandbox_pwm_set_config()
69 chan->duty_ns = duty_ns; in sandbox_pwm_set_config()
83 chan = &priv->chan[channel]; in sandbox_pwm_set_enable()
84 chan->enable = enable; in sandbox_pwm_set_enable()
97 chan = &priv->chan[channel]; in sandbox_pwm_set_invert()
[all …]
/u-boot/drivers/ddr/marvell/a38x/
A Dxor.c185 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
188 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_mem_init()
200 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
216 reg_bit_set(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
306 (XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_command_set()
312 (XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_command_set()
319 (XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_command_set()
325 (XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_command_set()
415 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_transfer()
451 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_transfer()
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A Dxor_regs.h13 #define XOR_UNIT(chan) ((chan) >> 1) argument
14 #define XOR_CHAN(chan) ((chan) & 1) argument
22 (0x10 + ((chan) * 4)))
24 (0x20 + ((chan) * 4)))
38 (0x220 + ((chan) * 4)))
42 (0x2b0 + ((chan) * 4)))
44 (0x2c0 + ((chan) * 4)))
99 #define XEICR_CAUSE_OFFS(chan) (chan * XEICR_CHAN_OFFS) argument
100 #define XEICR_CAUSE_MASK(chan, cause) (1 << (cause + XEICR_CAUSE_OFFS(chan))) argument
102 #define XEICR_COMP_MASK(chan) (0x000f << XEICR_CAUSE_OFFS(chan)) argument
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A Dxor.h82 enum mv_state mv_xor_state_get(u32 chan);
84 int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
85 int mv_xor_command_set(u32 chan, enum mv_command command);
86 int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
88 int mv_xor_transfer(u32 chan, enum xor_type type, u32 xor_chain_ptr);
/u-boot/drivers/firmware/scmi/
A Dmailbox_agent.c54 ret = mbox_send(&chan->mbox, chan->smt.buf); in scmi_mbox_process_msg()
61 ret = mbox_recv(&chan->mbox, chan->smt.buf, chan->timeout_us); in scmi_mbox_process_msg()
70 scmi_clear_smt_channel(&chan->smt); in scmi_mbox_process_msg()
91 chan->timeout_us = TIMEOUT_US_10MS; in setup_channel()
100 struct scmi_mbox_channel *chan; in scmi_mbox_get_channel() local
110 chan = calloc(1, sizeof(*chan)); in scmi_mbox_get_channel()
111 if (!chan) in scmi_mbox_get_channel()
115 ret = setup_channel(dev, chan); in scmi_mbox_get_channel()
117 free(chan); in scmi_mbox_get_channel()
121 *channel = (void *)chan; in scmi_mbox_get_channel()
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A Dsmccc_agent.c45 struct scmi_smccc_channel *chan = &channel->ref; in scmi_smccc_process_msg() local
49 ret = scmi_write_msg_to_smt(dev, &chan->smt, msg); in scmi_smccc_process_msg()
59 scmi_clear_smt_channel(&chan->smt); in scmi_smccc_process_msg()
74 chan->func_id = func_id; in setup_channel()
76 ret = scmi_dt_get_smt_buffer(dev, &chan->smt); in setup_channel()
87 struct scmi_smccc_channel *chan; in scmi_smccc_get_channel() local
99 chan = calloc(1, sizeof(*chan)); in scmi_smccc_get_channel()
100 if (!chan) in scmi_smccc_get_channel()
103 ret = setup_channel(dev, chan); in scmi_smccc_get_channel()
105 free(chan); in scmi_smccc_get_channel()
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A Doptee_agent.c172 if (chan->dyn_shm) in open_channel()
253 if (!chan->dyn_shm) in prepare_shm()
256 chan->smt.size = SCMI_SHM_SIZE; in prepare_shm()
273 if (chan->dyn_shm) in release_shm()
318 chan->dyn_shm = false; in setup_channel()
320 chan->dyn_shm = true; in setup_channel()
330 struct scmi_optee_channel *chan; in scmi_optee_get_channel() local
342 chan = calloc(1, sizeof(*chan)); in scmi_optee_get_channel()
343 if (!chan) in scmi_optee_get_channel()
346 ret = setup_channel(dev, chan); in scmi_optee_get_channel()
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/u-boot/drivers/mailbox/
A Dstm32-ipcc.c32 #define RX_BIT_CHAN(chan) BIT(chan) argument
34 #define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan)) argument
47 struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); in stm32_ipcc_request()
49 dev_dbg(chan->dev, "chan=%p\n", chan); in stm32_ipcc_request()
51 if (chan->id >= ipcc->n_chans) { in stm32_ipcc_request()
53 chan->id); in stm32_ipcc_request()
60 static int stm32_ipcc_free(struct mbox_chan *chan) in stm32_ipcc_free() argument
62 dev_dbg(chan->dev, "chan=%p\n", chan); in stm32_ipcc_free()
71 dev_dbg(chan->dev, "chan=%p, data=%p\n", chan, data); in stm32_ipcc_send()
88 dev_dbg(chan->dev, "chan=%p, data=%p\n", chan, data); in stm32_ipcc_recv()
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A Dmailbox-uclass.c24 debug("%s(chan=%p)\n", __func__, chan); in mbox_of_xlate_default()
31 chan->id = args->args[0]; in mbox_of_xlate_default()
70 chan->dev = dev_mbox; in mbox_get_by_index()
72 ret = ops->of_xlate(chan, &args); in mbox_get_by_index()
81 ret = ops->request(chan); in mbox_get_by_index()
91 struct mbox_chan *chan) in mbox_get_by_name() argument
106 int mbox_free(struct mbox_chan *chan) in mbox_free() argument
110 debug("%s(chan=%p)\n", __func__, chan); in mbox_free()
113 return ops->rfree(chan); in mbox_free()
124 return ops->send(chan, data); in mbox_send()
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A Dsandbox-mbox.c25 static int sandbox_mbox_request(struct mbox_chan *chan) in sandbox_mbox_request() argument
27 debug("%s(chan=%p)\n", __func__, chan); in sandbox_mbox_request()
29 if (chan->id >= SANDBOX_MBOX_CHANNELS) in sandbox_mbox_request()
35 static int sandbox_mbox_free(struct mbox_chan *chan) in sandbox_mbox_free() argument
37 debug("%s(chan=%p)\n", __func__, chan); in sandbox_mbox_free()
44 struct sandbox_mbox *sbm = dev_get_priv(chan->dev); in sandbox_mbox_send()
50 sbm->chans[chan->id].rx_msg_valid = true; in sandbox_mbox_send()
57 struct sandbox_mbox *sbm = dev_get_priv(chan->dev); in sandbox_mbox_recv()
62 if (!sbm->chans[chan->id].rx_msg_valid) in sandbox_mbox_recv()
65 *pmsg = sbm->chans[chan->id].rx_msg; in sandbox_mbox_recv()
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A Dtegra-hsp.c77 debug("%s(chan=%p)\n", __func__, chan); in tegra_hsp_of_xlate()
84 chan->id = (args->args[0] << 16) | args->args[1]; in tegra_hsp_of_xlate()
89 static int tegra_hsp_request(struct mbox_chan *chan) in tegra_hsp_request() argument
93 debug("%s(chan=%p)\n", __func__, chan); in tegra_hsp_request()
95 db_id = tegra_hsp_db_id(chan->id); in tegra_hsp_request()
104 static int tegra_hsp_free(struct mbox_chan *chan) in tegra_hsp_free() argument
106 debug("%s(chan=%p)\n", __func__, chan); in tegra_hsp_free()
113 struct tegra_hsp *thsp = dev_get_priv(chan->dev); in tegra_hsp_send()
118 db_id = tegra_hsp_db_id(chan->id); in tegra_hsp_send()
126 struct tegra_hsp *thsp = dev_get_priv(chan->dev); in tegra_hsp_recv()
[all …]
A Dk3-sec-proxy.c84 struct mbox_chan chan; member
116 debug("%s(chan=%p)\n", __func__, chan); in k3_sec_proxy_of_xlate()
126 chan->id = ind; in k3_sec_proxy_of_xlate()
127 chan->con_priv = &spm->chans[i]; in k3_sec_proxy_of_xlate()
141 debug("%s(chan=%p)\n", __func__, chan); in k3_sec_proxy_request()
152 debug("%s(chan=%p)\n", __func__, chan); in k3_sec_proxy_free()
207 struct k3_sec_proxy_thread *spt = chan->con_priv; in k3_sec_proxy_send()
216 dev_err(chan->dev, in k3_sec_proxy_send()
224 dev_err(chan->dev, in k3_sec_proxy_send()
255 __func__, chan->id); in k3_sec_proxy_send()
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A Dsandbox-mbox-test.c13 struct mbox_chan chan; member
20 return mbox_get_by_name(dev, "test", &sbmt->chan); in sandbox_mbox_test_get()
27 return mbox_send(&sbmt->chan, &msg); in sandbox_mbox_test_send()
34 return mbox_recv(&sbmt->chan, msg, 100); in sandbox_mbox_test_recv()
41 return mbox_free(&sbmt->chan); in sandbox_mbox_test_free()
/u-boot/drivers/timer/
A Datmel_tcb_timer.c15 #define TCB_CHAN(chan) ((chan) * 0x40) argument
17 #define TCB_CCR(chan) (0x0 + TCB_CHAN(chan)) argument
20 #define TCB_CMR(chan) (0x4 + TCB_CHAN(chan)) argument
27 #define TCB_CV(chan) (0x10 + TCB_CHAN(chan)) argument
29 #define TCB_RA(chan) (0x14 + TCB_CHAN(chan)) argument
30 #define TCB_RC(chan) (0x1c + TCB_CHAN(chan)) argument
32 #define TCB_IDR(chan) (0x28 + TCB_CHAN(chan)) argument
/u-boot/include/
A Dmailbox-uclass.h37 int (*of_xlate)(struct mbox_chan *chan,
50 int (*request)(struct mbox_chan *chan);
59 int (*rfree)(struct mbox_chan *chan);
67 int (*send)(struct mbox_chan *chan, const void *data);
79 int (*recv)(struct mbox_chan *chan, void *data);
A Dmailbox.h81 int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan);
100 struct mbox_chan *chan);
109 int mbox_free(struct mbox_chan *chan);
125 int mbox_send(struct mbox_chan *chan, const void *data);
145 int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us);
/u-boot/drivers/ram/rockchip/
A Dsdram_rk3066.c39 struct rk3066_dmc_chan_info chan[1]; member
525 unsigned int chan; in rk3066_dmc_dram_all_config() local
530 for (chan = 0; chan < sdram_params->num_channels; chan++) { in rk3066_dmc_dram_all_config()
532 &sdram_params->ch[chan]; in rk3066_dmc_dram_all_config()
544 rk3066_dmc_dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in rk3066_dmc_dram_all_config()
559 const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; in rk3066_dmc_sdram_rank_bw_detect() local
612 const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; in rk3066_dmc_sdram_col_row_detect() local
637 writel(1, &chan->msch->ddrconf); in rk3066_dmc_sdram_col_row_detect()
704 const struct rk3066_dmc_chan_info *chan = &dram->chan[channel]; in rk3066_dmc_sdram_init() local
748 writel(1, &chan->msch->ddrconf); in rk3066_dmc_sdram_init()
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A Dsdram_rk3188.c38 struct chan_info chan[1]; member
539 unsigned int chan; in dram_all_config() local
544 for (chan = 0; chan < sdram_params->num_channels; chan++) { in dram_all_config()
546 &sdram_params->ch[chan]; in dram_all_config()
558 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
573 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect() local
634 const struct chan_info *chan = &dram->chan[channel]; in sdram_col_row_detect() local
659 writel(1, &chan->msch->ddrconf); in sdram_col_row_detect()
660 move_to_access_state(chan); in sdram_col_row_detect()
733 const struct chan_info *chan = &dram->chan[channel]; in sdram_init() local
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A Dsdram_rk3399.c70 struct chan_info chan[2]; member
1380 struct chan_info *chan = &dram->chan[channel]; in data_training() local
1811 struct chan_info *chan = &dram->chan[channel]; in lpddr4_mr_detect() local
2675 const struct chan_info *chan = &dram->chan[channel]; in dram_detect_cap() local
2688 dram_set_bw(chan, bw); in dram_detect_cap()
2693 dram_set_bw(chan, 1); in dram_detect_cap()
2967 const struct chan_info *chan = &dram->chan[channel]; in sdram_init() local
3111 priv->chan[0].pctl, priv->chan[0].pi, in rk3399_dmc_init()
3112 priv->chan[0].publ, priv->chan[0].msch, in rk3399_dmc_init()
3113 priv->chan[1].pctl, priv->chan[1].pi, in rk3399_dmc_init()
[all …]
A Dsdram_rk3288.c40 struct chan_info chan[2]; member
597 unsigned int chan; in dram_all_config() local
602 for (chan = 0; chan < sdram_params->num_channels; chan++) { in dram_all_config()
604 &sdram_params->ch[chan]; in dram_all_config()
616 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
627 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect() local
680 const struct chan_info *chan = &dram->chan[channel]; in sdram_col_row_detect() local
704 writel(4, &chan->msch->ddrconf); in sdram_col_row_detect()
705 move_to_access_state(chan); in sdram_col_row_detect()
810 const struct chan_info *chan = &dram->chan[channel]; in sdram_init() local
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/u-boot/arch/arm/include/asm/arch-omap3/
A Ddma.h11 int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
13 int omap3_dma_start_transfer(uint32_t chan);
14 int omap3_dma_wait_for_transfer(uint32_t chan);
15 int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
16 int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
/u-boot/drivers/dma/
A Dapbh_dma.c510 ret = mxs_dma_validate_chan(chan); in mxs_dma_wait_complete()
515 1 << chan, timeout)) { in mxs_dma_wait_complete()
517 mxs_dma_reset(chan); in mxs_dma_wait_complete()
526 int mxs_dma_go(int chan) in mxs_dma_go() argument
533 mxs_dma_enable_irq(chan, 1); in mxs_dma_go()
534 mxs_dma_enable(chan); in mxs_dma_go()
543 mxs_dma_ack_irq(chan); in mxs_dma_go()
544 mxs_dma_reset(chan); in mxs_dma_go()
545 mxs_dma_enable_irq(chan, 0); in mxs_dma_go()
546 mxs_dma_disable(chan); in mxs_dma_go()
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/u-boot/arch/arm/mach-apple/
A Drtkit.c58 struct mbox_chan *chan; member
78 rtk->chan = chan; in apple_rtkit_init()
146 return mbox_send(rtk->chan, msg); in rtkit_handle_buf_req()
168 ret = mbox_send(rtk->chan, &msg); in apple_rtkit_boot()
173 ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US); in apple_rtkit_boot()
209 ret = mbox_send(rtk->chan, &msg); in apple_rtkit_boot()
215 ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US); in apple_rtkit_boot()
246 ret = mbox_send(rtk->chan, &msg); in apple_rtkit_boot()
273 ret = mbox_send(rtk->chan, &msg); in apple_rtkit_boot()
301 ret = mbox_send(rtk->chan, &msg); in apple_rtkit_boot()
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