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Searched refs:clk_base (Results 1 – 3 of 3) sorted by relevance

/u-boot/board/hisilicon/hikey/
A Dhikey.c155 void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base) in hi6220_clk_enable() argument
159 data = readl(clk_base); in hi6220_clk_enable()
162 writel(bitfield, clk_base); in hi6220_clk_enable()
164 data = readl(clk_base + STAT_EN_OFF); in hi6220_clk_enable()
171 void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base) in hi6220_clk_disable() argument
175 data = readl(clk_base); in hi6220_clk_disable()
178 writel(data, clk_base); in hi6220_clk_disable()
180 data = readl(clk_base + STAT_DIS_OFF); in hi6220_clk_disable()
/u-boot/board/freescale/t208xqds/
A Dt208xqds.c332 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_sys_clk()
370 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_ddr_clk()
/u-boot/board/freescale/common/
A Dqixis.h86 u8 clk_base[2]; /* Clock Frequency Base Reg */ member

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