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Searched refs:clk_div_mask (Results 1 – 6 of 6) sorted by relevance

/u-boot/drivers/clk/
A Dclk-divider.c54 return val ? val : clk_div_mask(width) + 1; in _get_div()
90 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()
136 return (div == clk_div_mask(width) + 1) ? 0 : div; in _get_val()
154 return min_t(unsigned int, value, clk_div_mask(width)); in divider_get_val()
170 val = clk_div_mask(divider->width) << (divider->shift + 16); in clk_divider_set_rate()
173 val &= ~(clk_div_mask(divider->width) << divider->shift); in clk_divider_set_rate()
A Dclk_sandbox_ccf.c159 val &= clk_div_mask(divider->width); in sandbox_clk_composite_divider_recalc_rate()
/u-boot/drivers/clk/microchip/
A Dmpfs_clk_msspll.c67 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
69 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
71 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
A Dmpfs_clk_cfg.c77 val &= clk_div_mask(cfg->width); in mpfs_cfg_clk_recalc_rate()
98 val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); in mpfs_cfg_clk_set_rate()
/u-boot/drivers/clk/imx/
A Dclk-composite-8m.c45 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
52 div_value &= clk_div_mask(PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
105 val &= ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()
106 (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); in imx8m_clk_composite_divider_set_rate()
/u-boot/include/linux/
A Dclk-provider.h129 #define clk_div_mask(width) ((1 << (width)) - 1) macro

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