Home
last modified time | relevance | path

Searched refs:core (Results 1 – 25 of 410) sorted by relevance

12345678910>>...17

/u-boot/drivers/remoteproc/
A Dti_k3_r5f_rproc.c124 return core == core->cluster->cores[0]; in is_primary_core()
286 memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size); in k3_r5f_init_tcm_memories()
288 memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size); in k3_r5f_init_tcm_memories()
685 ret = ti_sci_proc_of_to_priv(core->dev, &core->tsp); in k3_r5f_of_to_priv()
689 ret = reset_get_by_index(core->dev, 0, &core->reset); in k3_r5f_of_to_priv()
709 core->mem = calloc(core->num_mems, sizeof(*core->mem)); in k3_r5f_core_of_get_memories()
726 core->mem[i].dev_addr = core->loczrama ? in k3_r5f_core_of_get_memories()
729 core->mem[i].dev_addr = core->loczrama ? in k3_r5f_core_of_get_memories()
735 core->mem[i].size, core->mem[i].cpu_addr, in k3_r5f_core_of_get_memories()
770 core->mem[0].size, core->mem[1].size); in k3_r5f_core_adjust_tcm_sizes()
[all …]
/u-boot/arch/mips/mach-octeon/include/mach/
A Dcvmx-coremask.h94 for ((core) = -1; \
95 (core) = cvmx_coremask_next_core((core), pcm), \
96 (core) >= 0;)
138 int core) in cvmx_coremask_is_core_set() argument
142 n = core % CVMX_COREMASK_HLDRSZ; in cvmx_coremask_is_core_set()
143 i = core / CVMX_COREMASK_HLDRSZ; in cvmx_coremask_is_core_set()
186 n = core % CVMX_COREMASK_HLDRSZ; in cvmx_coremask_set_core()
525 core++; in cvmx_coremask_next_core()
565 assert(core < CVMX_MAX_CORES); in cvmx_coremask_set_cores()
577 core = 0; in cvmx_coremask_set_cores()
[all …]
/u-boot/drivers/phy/
A Dphy-bcm-sr-pcie.c96 pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET); in pipemux_strap_read()
99 pipemux = readl(core->cdru + CDRU_STRAP_DATA_LSW_OFFSET); in pipemux_strap_read()
109 struct sr_pcie_phy_core *core = dev_get_priv(phy->dev); in sr_pcie_phy_init() local
118 if (!!((pipemux_table[core->pipemux] >> core_idx) & 0x1)) in sr_pcie_phy_init()
142 struct sr_pcie_phy_core *core = dev_get_priv(dev); in sr_pcie_phy_probe() local
144 core->dev = dev; in sr_pcie_phy_probe()
148 debug("ip base %p\n", core->base); in sr_pcie_phy_probe()
149 debug("cdru base %p\n", core->cdru); in sr_pcie_phy_probe()
152 core->pipemux = pipemux_strap_read(core); in sr_pcie_phy_probe()
153 if (!pipemux_strap_is_valid(core->pipemux)) { in sr_pcie_phy_probe()
[all …]
/u-boot/drivers/clk/renesas/
A Dclk-rcar-gen3.c63 const struct cpg_core_clk *core; in gen3_clk_get_parent() local
75 parent->id = core->parent >> shift; in gen3_clk_get_parent()
104 const struct cpg_core_clk *core; in gen3_clk_setup_sdif_div() local
137 switch (core->type) { in gen3_clk_setup_sdif_div()
189 const struct cpg_core_clk *core; in gen3_clk_get_rate64() local
218 switch (core->type) { in gen3_clk_get_rate64()
284 core->offset, 0, 0, "PLL2X_3X"); in gen3_clk_get_rate64()
312 0, core->mult, core->div, in gen3_clk_get_rate64()
341 priv->base + core->offset, in gen3_clk_get_rate64()
355 priv->base + core->offset, in gen3_clk_get_rate64()
[all …]
A Dclk-rcar-gen2.c75 const struct cpg_core_clk *core; in gen2_clk_get_rate() local
100 switch (core->type) { in gen2_clk_get_rate()
102 if (core->id == info->clk_extal_id) { in gen2_clk_get_rate()
119 rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div; in gen2_clk_get_rate()
122 core->parent, core->mult, core->div, rate); in gen2_clk_get_rate()
130 core->parent, value, rate); in gen2_clk_get_rate()
178 core->parent, div, rate); in gen2_clk_get_rate()
187 core->parent, div, rate); in gen2_clk_get_rate()
196 core->parent, div, rate); in gen2_clk_get_rate()
209 const struct cpg_core_clk *core; in gen2_clk_setup_mmcif_div() local
[all …]
A Drenesas-cpg-mssr.c49 const struct cpg_core_clk **core) in renesas_clk_get_core() argument
58 *core = &info->core_clk[i]; in renesas_clk_get_core()
68 const struct cpg_core_clk *core; in renesas_clk_get_parent() local
79 ret = renesas_clk_get_core(clk, info, &core); in renesas_clk_get_parent()
83 if (core->type == CLK_TYPE_IN) in renesas_clk_get_parent()
86 parent->id = core->parent; in renesas_clk_get_parent()
/u-boot/arch/mips/mach-octeon/
A Dbootoctlinux.c372 int core; in do_bootoctlinux() local
497 cvmx_bootinfo_array[core].core_mask = in do_bootoctlinux()
502 if (core == first_core) in do_bootoctlinux()
512 cvmx_bootinfo_array[core].phy_mem_desc_addr = in do_bootoctlinux()
521 boot_desc[core].cvmx_desc_vaddr = in do_bootoctlinux()
522 virt_to_phys(&cvmx_bootinfo_array[core]); in do_bootoctlinux()
527 boot_desc[core].flags = cvmx_bootinfo_array[core].flags; in do_bootoctlinux()
528 boot_desc[core].eclock_hz = cvmx_bootinfo_array[core].eclock_hz; in do_bootoctlinux()
530 boot_desc[core].argc = argc; in do_bootoctlinux()
535 core = 0; in do_bootoctlinux()
[all …]
A Dcvmx-coremask.c79 static int convert_ciu_fuse_to_physical_core(int core, int max_cores) in convert_ciu_fuse_to_physical_core() argument
82 return core; in convert_ciu_fuse_to_physical_core()
84 return core; in convert_ciu_fuse_to_physical_core()
85 else if (core < (max_cores / 2)) in convert_ciu_fuse_to_physical_core()
86 return core * 2; in convert_ciu_fuse_to_physical_core()
88 return ((core - (max_cores / 2)) * 2) + 1; in convert_ciu_fuse_to_physical_core()
104 int core, physical_core; in fill_tad_corecount() local
106 for (core = 0; core < max_cores; core++) { in fill_tad_corecount()
107 if (!(coremask & (1ULL << core))) { in fill_tad_corecount()
111 convert_ciu_fuse_to_physical_core(core, in fill_tad_corecount()
/u-boot/arch/arm/mach-omap2/omap4/
A Dhw_data.c192 .core = core_dpll_params_1600mhz,
206 .core = core_dpll_params_1600mhz,
220 .core = core_dpll_params_1600mhz,
269 .core.value[OPP_NOM] = 1200,
271 .core.pmic = &twl6030_4430es1,
283 .core.value[OPP_NOM] = 1200,
285 .core.pmic = &twl6030,
297 .core.value[OPP_NOM] = 1200,
299 .core.pmic = &twl6030,
315 .core.value[OPP_NOM] = 1126,
[all …]
/u-boot/arch/arm/mach-tegra/tegra20/
A Dpmu.c32 int core, cpu; in pmu_set_nominal() local
38 core = VDD_CORE_NOMINAL_T20; in pmu_set_nominal()
42 core = VDD_CORE_NOMINAL_T25; in pmu_set_nominal()
63 return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP, in pmu_set_nominal()
/u-boot/board/google/chameleonv3/
A Dfpga_early_io.its19 fpga-core-1 {
20 description = "FPGA core bitstream";
21 data = /incbin/("../../../core.rbf");
32 fpga = "fpga-periph-1", "fpga-core-1";
/u-boot/board/altera/arria10-socdk/
A Dfit_spl_fpga.its22 fpga-core-1 {
23 description = "FPGA core bitstream";
24 data = /incbin/("../../../ghrd_10as066n2.core.rbf");
35 fpga = "fpga-periph-1", "fpga-core-1";
/u-boot/arch/arm/mach-imx/imx9/
A Dimx_bootaux.c67 u32 core = 0; in do_bootaux() local
74 core = simple_strtoul(argv[2], NULL, 10); in do_bootaux()
79 up = arch_auxiliary_core_check_up(core); in do_bootaux()
90 ret = arch_auxiliary_core_up(core, addr); in do_bootaux()
/u-boot/arch/arm/dts/
A Dpx30-engicam-px30-core-ctouch2.dts12 #include "px30-engicam-px30-core.dtsi"
16 compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
A Dpx30-engicam-px30-core-edimm2.2.dts11 #include "px30-engicam-px30-core.dtsi"
15 compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
A Dpx30-engicam-px30-core-ctouch2-of10.dts11 #include "px30-engicam-px30-core.dtsi"
15 compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
/u-boot/board/engicam/px30_core/
A DMAINTAINERS5 F: configs/px30-core-ctouch2-px30_defconfig
11 F: configs/px30-core-ctouch2-of10-px30_defconfig
19 F: configs/px30-core-edimm2.2-px30_defconfig
/u-boot/drivers/usb/gadget/udc/
A DMakefile6 obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o
9 obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-core.o
/u-boot/arch/arm/mach-omap2/omap5/
A Dhw_data.c220 .core = core_dpll_params_2128mhz_ddr532,
234 .core = core_dpll_params_2128mhz_ddr532_es2,
248 .core = core_dpll_params_2128mhz_dra7xx,
259 .core = core_dpll_params_2128mhz_dra7xx,
270 .core = core_dpll_params_2128mhz_dra7xx,
345 .core.value[OPP_NOM] = VDD_CORE,
346 .core.addr = SMPS_REG_ADDR_8_CORE,
347 .core.pmic = &palmas,
360 .core.value[OPP_NOM] = VDD_CORE_ES2,
361 .core.addr = SMPS_REG_ADDR_8_CORE,
[all …]
/u-boot/board/ti/dra7xx/
A Devm.c410 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
413 .core.addr = TPS659038_REG_ADDR_SMPS7,
414 .core.pmic = &tps659038,
458 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
461 .core.addr = TPS65917_REG_ADDR_SMPS3,
462 .core.pmic = &tps659038,
484 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
487 .core.addr = TPS65917_REG_ADDR_SMPS2,
488 .core.pmic = &tps659038,
543 .core.addr = LP873X_REG_ADDR_BUCK0,
[all …]
/u-boot/arch/arm/mach-mediatek/
A DKconfig19 The MediaTek MT7622 is a ARM64-based SoC with a dual-core Cortex-A53.
27 The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7
39 The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7
48 The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53.
57 The MediaTek MT7986 is a ARM64-based SoC with a quad-core Cortex-A53.
65 The MediaTek MT8183 is a ARM64-based SoC with a quad-core Cortex-A73 and
66 a quad-core Cortex-A53. It is including UART, SPI, USB3.0 dual role,
75 The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53.
84 The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35.
93 The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53.
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.core_prefetch3 To disable instruction prefetch of core; hwconfig needs to be updated.
8 represents 64 bit mask. The 64-bit Mask has one bit for each core.
14 that core when it is released from reset.
/u-boot/arch/x86/include/asm/
A Dintel_acpi.h42 void generate_p_state_entries(struct acpi_ctx *ctx, int core,
44 void generate_t_state_entries(struct acpi_ctx *ctx, int core,
/u-boot/board/armltd/integrator/
A DREADME14 Each may be fitted with a variety of core modules (CMs).
15 Each CM consists of a ARM processor core and associated hardware e.g
50 However, to avoid duplicating code through all processor files, a generic core
66 The U-Boot make targets map to the available core modules as below.
80 The final groups of targets are for core modules where no explicit cpu
82 using the generic "arm_intcm" core:
101 to indicate the core module & core configuration and ensure that
/u-boot/doc/device-tree-bindings/fpga/
A Daltera-socfpga-a10-fpga-mgr.txt11 FPGA core bitstream and full bitstream.
13 Full bitstream, consist of peripheral bitstream and core
20 FPGA core bitstream contains FPGA design which is used to
23 Example: Bundles both peripheral bitstream and core bitstream into FIT image

Completed in 49 milliseconds

12345678910>>...17