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Searched refs:cr (Results 1 – 25 of 137) sorted by relevance

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/u-boot/arch/arm/mach-imx/
A Dddrmc-vf610.c131 &ddrmr->cr[13]); in ddrmc_ctrl_init_ddr3()
142 writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); in ddrmc_ctrl_init_ddr3()
145 &ddrmr->cr[21]); in ddrmc_ctrl_init_ddr3()
152 writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); in ddrmc_ctrl_init_ddr3()
187 &ddrmr->cr[74]); in ddrmc_ctrl_init_ddr3()
189 DDRMC_CR75_PLEN, &ddrmr->cr[75]); in ddrmc_ctrl_init_ddr3()
191 DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); in ddrmc_ctrl_init_ddr3()
193 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); in ddrmc_ctrl_init_ddr3()
197 writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); in ddrmc_ctrl_init_ddr3()
201 &ddrmr->cr[87]); in ddrmc_ctrl_init_ddr3()
[all …]
A Dddrmc-vf610-calibration.c159 writel(0x40703030, &ddrmr->cr[144]); in ddrmc_cal_dqs_to_dq()
160 writel(0x40, &ddrmr->cr[145]); in ddrmc_cal_dqs_to_dq()
161 writel(0x40, &ddrmr->cr[146]); in ddrmc_cal_dqs_to_dq()
163 tmp = readl(&ddrmr->cr[144]); in ddrmc_cal_dqs_to_dq()
169 tmp = readl(&ddrmr->cr[145]); in ddrmc_cal_dqs_to_dq()
172 tmp = readl(&ddrmr->cr[146]); in ddrmc_cal_dqs_to_dq()
183 tmp = readl(&ddrmr->cr[101]); in ddrmc_cal_dqs_to_dq()
190 tmp = readl(&ddrmr->cr[93]); in ddrmc_cal_dqs_to_dq()
210 clrsetbits_le32(&ddrmr->cr[105], in ddrmc_cal_dqs_to_dq()
226 swlvl_rsp = (readl(&ddrmr->cr[94]) >> in ddrmc_cal_dqs_to_dq()
[all …]
/u-boot/arch/arm/mach-at91/
A Dmpddrc.c46 u32 ba_off, cr; in ddr2_init() local
59 writel(mpddr_value->cr, &mpddr->cr); in ddr2_init()
94 cr = readl(&mpddr->cr); in ddr2_init()
95 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); in ddr2_init()
108 cr = readl(&mpddr->cr); in ddr2_init()
115 cr = readl(&mpddr->cr); in ddr2_init()
116 writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr); in ddr2_init()
126 cr = readl(&mpddr->cr); in ddr2_init()
127 writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr); in ddr2_init()
169 writel(mpddr_value->cr, &mpddr->cr); in ddr3_init()
[all …]
/u-boot/drivers/timer/
A Dfttmr010_timer.c41 unsigned int cr; in fttmr010_timer_probe() local
51 writel(0, &tmr->cr); in fttmr010_timer_probe()
65 cr = readl(&tmr->cr); in fttmr010_timer_probe()
66 cr |= FTTMR010_TM3_CLOCK; /* use external clock */ in fttmr010_timer_probe()
67 cr |= FTTMR010_TM3_ENABLE; in fttmr010_timer_probe()
68 writel(cr, &tmr->cr); in fttmr010_timer_probe()
A Dimx-gpt-timer.c37 u32 cr; member
66 setbits_le32(&regs->cr, GPT_CR_SWR); in imx_gpt_setup()
69 while (readl(&regs->cr) & GPT_CR_SWR) in imx_gpt_setup()
82 writel(GPT_CLKSRC_IPG_CLK_24M | GPT_CR_EN_24M | GPT_CR_FRR, &regs->cr); in imx_gpt_setup()
92 writel(GPT_CLKSRC_IPG_CLK | GPT_CR_FRR, &regs->cr); in imx_gpt_setup()
96 setbits_le32(&regs->cr, GPT_CR_EN); in imx_gpt_setup()
/u-boot/post/lib_powerpc/
A Dcr.c50 ulong cr; member
65 ulong cr; member
88 ulong cr; member
237 ulong cr = cpu_post_cr_table1[i]; in cpu_post_test_cr() local
247 cpu_post_exec_11 (code, &res, cr); in cpu_post_test_cr()
249 ret = res == cr ? 0 : -1; in cpu_post_test_cr()
266 ASM_MCRXR(test->cr), in cpu_post_test_cr()
274 ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ? in cpu_post_test_cr()
296 cpu_post_exec_11 (code, &res, test->cr); in cpu_post_test_cr()
319 cpu_post_exec_11 (code, &res, test->cr); in cpu_post_test_cr()
A Dsrawi.c24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
100 ulong cr; in cpu_post_test_srawi() local
104 cr = 0; in cpu_post_test_srawi()
105 cpu_post_exec_21 (code, & cr, & res, test->op1); in cpu_post_test_srawi()
107 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_srawi()
117 cpu_post_exec_21 (codecr, & cr, & res, test->op1); in cpu_post_test_srawi()
120 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_srawi()
A Dtwo.c27 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
120 ulong cr; in cpu_post_test_two() local
124 cr = 0; in cpu_post_test_two()
125 cpu_post_exec_21 (code, & cr, & res, test->op); in cpu_post_test_two()
127 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_two()
137 cpu_post_exec_21 (codecr, & cr, & res, test->op); in cpu_post_test_two()
140 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_two()
A Dtwox.c27 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
120 ulong cr; in cpu_post_test_twox() local
124 cr = 0; in cpu_post_test_twox()
125 cpu_post_exec_21 (code, & cr, & res, test->op); in cpu_post_test_twox()
127 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_twox()
137 cpu_post_exec_21 (codecr, & cr, & res, test->op); in cpu_post_test_twox()
140 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_twox()
A Drlwinm.c24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
99 ulong cr; in cpu_post_test_rlwinm() local
103 cr = 0; in cpu_post_test_rlwinm()
104 cpu_post_exec_21 (code, & cr, & res, test->op1); in cpu_post_test_rlwinm()
106 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_rlwinm()
116 cpu_post_exec_21 (codecr, & cr, & res, test->op1); in cpu_post_test_rlwinm()
119 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_rlwinm()
A Dcpu.c47 ulong cr = 0; in cpu_post_makecr() local
50 cr |= 0x80000000; in cpu_post_makecr()
52 cr |= 0x40000000; in cpu_post_makecr()
54 cr |= 0x20000000; in cpu_post_makecr()
56 return cr; in cpu_post_makecr()
A Drlwnm.c24 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
109 ulong cr; in cpu_post_test_rlwnm() local
113 cr = 0; in cpu_post_test_rlwnm()
114 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_rlwnm()
116 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_rlwnm()
126 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_rlwnm()
129 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_rlwnm()
A Drlwimi.c24 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
106 ulong cr; in cpu_post_test_rlwimi() local
110 cr = 0; in cpu_post_test_rlwimi()
111 cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1); in cpu_post_test_rlwimi()
113 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_rlwimi()
123 cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1); in cpu_post_test_rlwimi()
126 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_rlwimi()
A Dthreex.c27 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
173 ulong cr; in cpu_post_test_threex() local
177 cr = 0; in cpu_post_test_threex()
178 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_threex()
180 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_threex()
190 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_threex()
193 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_threex()
A Dthreei.c26 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
97 ulong cr; in cpu_post_test_threei() local
99 cr = 0; in cpu_post_test_threei()
100 cpu_post_exec_21 (code, & cr, & res, test->op1); in cpu_post_test_threei()
102 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_threei()
A Dthree.c27 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
203 ulong cr; in cpu_post_test_three() local
207 cr = 0; in cpu_post_test_three()
208 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_three()
210 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_three()
220 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_three()
223 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_three()
A Dandi.c24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
83 ulong cr; in cpu_post_test_andi() local
85 cpu_post_exec_21 (codecr, & cr, & res, test->op1); in cpu_post_test_andi()
88 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_andi()
A Db.c31 ulong cr);
34 int pjump, int decr, int link, ulong pctr, ulong cr) in cpu_post_test_bc() argument
56 cpu_post_exec_31 (code, &ctr, &lr, &jump, cr); in cpu_post_test_bc()
150 int cr = cond ? 0x80000000 : 0x00000000; in cpu_post_test_b() local
161 ctr, cr); in cpu_post_test_b()
A Dcmp.c35 ulong cr; member
95 ASM_2C(test->cmd, test->cr, 3, 4), in cpu_post_test_cmp()
103 ret = ((res >> (28 - 4 * test->cr)) & 0xe) == test->res ? 0 : -1; in cpu_post_test_cmp()
A Dcmpi.c35 ulong cr; member
95 ASM_1IC(test->cmd, test->cr, 3, test->op2), in cpu_post_test_cmpi()
103 ret = ((res >> (28 - 4 * test->cr)) & 0xe) == test->res ? 0 : -1; in cpu_post_test_cmpi()
/u-boot/drivers/rng/
A Dstm32mp1_rng.c92 u32 cr, sr; in stm32_rng_init() local
98 cr = readl(pdata->base + RNG_CR); in stm32_rng_init()
101 cr |= RNG_CR_CED; in stm32_rng_init()
103 cr |= RNG_CR_CONDRST; in stm32_rng_init()
104 writel(cr, pdata->base + RNG_CR); in stm32_rng_init()
105 cr &= ~RNG_CR_CONDRST; in stm32_rng_init()
106 writel(cr, pdata->base + RNG_CR); in stm32_rng_init()
107 err = readl_poll_timeout(pdata->base + RNG_CR, cr, in stm32_rng_init()
108 (!(cr & RNG_CR_CONDRST)), 10000); in stm32_rng_init()
116 cr |= RNG_CR_RNGEN; in stm32_rng_init()
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/u-boot/drivers/mtd/
A Dstm32_flash.c27 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK); in stm32_flash_lock()
102 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK); in flash_erase()
105 setbits_le32(&STM32_FLASH->cr, in flash_erase()
108 setbits_le32(&STM32_FLASH->cr, in flash_erase()
114 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); in flash_erase()
115 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT); in flash_erase()
120 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); in flash_erase()
136 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG); in write_buff()
147 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG); in write_buff()
/u-boot/drivers/spi/
A Dspi-sifive.c143 u32 cr; in sifive_spi_prep_transfer() local
149 cr &= ~SIFIVE_SPI_FMT_LEN_MASK; in sifive_spi_prep_transfer()
153 cr &= ~SIFIVE_SPI_FMT_ENDIAN; in sifive_spi_prep_transfer()
155 cr |= SIFIVE_SPI_FMT_ENDIAN; in sifive_spi_prep_transfer()
158 cr &= ~SIFIVE_SPI_FMT_PROTO_MASK; in sifive_spi_prep_transfer()
161 cr |= SIFIVE_SPI_FMT_PROTO_QUAD; in sifive_spi_prep_transfer()
172 cr &= ~SIFIVE_SPI_FMT_DIR; in sifive_spi_prep_transfer()
174 cr |= SIFIVE_SPI_FMT_DIR; in sifive_spi_prep_transfer()
364 u32 cr; in sifive_spi_set_mode() local
370 cr |= SIFIVE_SPI_SCKMODE_PHA; in sifive_spi_set_mode()
[all …]
A Dzynq_spi.c46 u32 cr; /* 0x00 */ member
117 writel(confr, &regs->cr); in zynq_spi_init_hw()
169 u32 cr; in spi_cs_activate() local
179 clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK); in spi_cs_activate()
180 cr = readl(&regs->cr); in spi_cs_activate()
188 writel(cr, &regs->cr); in spi_cs_activate()
201 setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK); in spi_cs_deactivate()
310 confr = readl(&regs->cr); in zynq_spi_set_speed()
324 writel(confr, &regs->cr); in zynq_spi_set_speed()
340 confr = readl(&regs->cr); in zynq_spi_set_mode()
[all …]
/u-boot/drivers/pwm/
A Dpwm-imx.c21 u32 cr; in pwm_config_internal() local
24 cr = PWMCR_PRESCALER(prescale) | in pwm_config_internal()
28 writel(cr, &pwm->cr); in pwm_config_internal()
135 setbits_le32(&pwm->cr, PWMCR_EN); in pwm_enable()
146 clrbits_le32(&pwm->cr, PWMCR_EN); in pwm_disable()
221 setbits_le32(&regs->cr, PWMCR_EN); in imx_pwm_set_enable()
223 clrbits_le32(&regs->cr, PWMCR_EN); in imx_pwm_set_enable()

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