Searched refs:csr_write (Results 1 – 7 of 7) sorted by relevance
| /u-boot/arch/riscv/cpu/ |
| A D | cpu.c | 105 csr_write(CSR_FCSR, 0); in riscv_cpu_setup()
115 csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0)); in riscv_cpu_setup()
116 csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0)); in riscv_cpu_setup()
118 csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); in riscv_cpu_setup()
127 csr_write(CSR_SATP, 0); in riscv_cpu_setup()
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| /u-boot/arch/sh/cpu/sh4/ |
| A D | watchdog.c | 27 static void csr_write(unsigned char value) in csr_write() function
42 csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE); in watchdog_init()
49 csr_write(csr_read() & ~WDT_ENABLE); in watchdog_disable()
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| /u-boot/arch/riscv/cpu/fu740/ |
| A D | spl.c | 37 csr_write(CSR_U74_FEATURE_DISABLE, 0); in harts_early_init()
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| /u-boot/arch/riscv/cpu/andesv5/ |
| A D | cpu.c | 39 csr_write(CSR_MCACHE_CTL, mcache_ctl_val); in harts_early_init()
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| A D | cache.c | 48 csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); in flush_dcache_all()
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| /u-boot/arch/riscv/cpu/jh7110/ |
| A D | spl.c | 42 csr_write(CSR_U74_FEATURE_DISABLE, 0); in harts_early_init()
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| /u-boot/arch/riscv/include/asm/ |
| A D | csr.h | 167 #define csr_write(csr, val) \ macro
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