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/u-boot/arch/mips/mach-ath79/ar934x/
A Dddr.c45 u32 reg, cycle, ctl; in ar934x_ddr_init() local
54 cycle = 0xffff; in ar934x_ddr_init()
60 cycle = 0xff; in ar934x_ddr_init()
62 cycle = 0xffff; in ar934x_ddr_init()
66 cycle = 0xffff; /* DDR2 16bit */ in ar934x_ddr_init()
83 cycle = 0xffffffff; in ar934x_ddr_init()
150 writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); in ar934x_ddr_init()
/u-boot/arch/arm/mach-npcm/npcm7xx/
A Dl2_cache_pl310_init.S35 @ 1 cycle RAM write access latency
36 @ 1 cycle RAM read access latency
37 @ 1 cycle RAM setup latency
42 @ 1 cycle RAM write access latency
44 @ 1 cycle RAM setup latency
/u-boot/board/atmel/at91sam9261ek/
A Dat91sam9261ek.c57 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
66 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
105 &smc->cs[2].cycle); in at91sam9261ek_dm9000_hw_init()
119 &smc->cs[2].cycle); in at91sam9261ek_dm9000_hw_init()
/u-boot/drivers/pwm/
A DKconfig6 control over the duty cycle (high and low time) of the signal. This
18 and duty cycle. It provides 16 channels which can be independently
48 supports a programmable period and duty cycle. A 32-bit counter is
62 programmable period and duty cycle for 2 independant channels.
69 programmable period and duty cycle.
76 programmable period and duty cycle. A 32-bit counter is used.
104 four channels with a programmable period and duty cycle. Only a
105 32KHz clock is supported by the driver but the duty cycle is
113 programmable period and duty cycle. A 16-bit counter is used.
/u-boot/drivers/mfd/
A Datmel-smc.c233 conf->cycle &= ~GENMASK(shift + 15, shift); in atmel_smc_cs_conf_set_cycle()
234 conf->cycle |= val << shift; in atmel_smc_cs_conf_set_cycle()
254 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle); in atmel_smc_cs_conf_apply()
275 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle); in atmel_hsmc_cs_conf_apply()
295 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle); in atmel_smc_cs_conf_get()
316 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle); in atmel_hsmc_cs_conf_get()
/u-boot/board/buffalo/lsxl/
A Dkwbimage-lschl.cfg38 # bit4: 0, addr/cmd in same cycle
55 # bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
56 # bit7-4: 4, 5 cycle tRCD
60 # bit20: 0, 16 cycle tRAS (tRAS[4])
62 # bit27-24: 3, 4 cycle tRRD
67 # bit6-0: 0x23, 35 cycle tRFC
68 # bit8-7: 0, 1 cycle tR2R
130 # bit9: 0, no half clock cycle addition to dataout
131 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
132 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
A Dkwbimage-lsxhl.cfg55 # bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
56 # bit7-4: 4, 5 cycle tRCD
60 # bit20: 1, 18 cycle tRAS (tRAS[4])
62 # bit27-24: 2, 3 cycle tRRD
67 # bit6-0: 0x32, 50 cycle tRFC
68 # bit8-7: 0, 1 cycle tR2R
130 # bit9: 0, no half clock cycle addition to dataout
131 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
132 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
/u-boot/board/d-link/dns325/
A Dkwbimage.cfg36 # bit4: 0, addr/cmd in smame cycle
52 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
53 # bit7-4: 5, 6 cycle tRCD
57 # bit20: 1, 18 cycle tRAS (tRAS[4])
59 # bit27-24: 2, 3 cycle tRRD
63 # bit6-0: 0x33, 33 cycle tRFC
64 # bit8-7: 0, 1 cycle tR2R
120 # bit9: 0, no half clock cycle addition to dataout
121 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
122 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
/u-boot/arch/arm/dts/
A Dsun50i-a64-pinephone-1.1.dts17 * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
18 * being off is around 20%. Duty cycle for the lowest brightness level
A Dsun50i-a64-pinephone-1.2.dts22 * and the lowest PWM duty cycle that doesn't lead to backlight being off
23 * is around 10%. Duty cycle for the lowest brightness level also varries
A Domap-gpmc-smsc911x.dtsi40 gpmc,rd-cycle-ns = <155>;
41 gpmc,wr-cycle-ns = <155>;
A Domap-gpmc-smsc9221.dtsi43 gpmc,rd-cycle-ns = <60>;
44 gpmc,wr-cycle-ns = <54>;
A Domap3-evm.dts78 gpmc,rd-cycle-ns = <82>;
79 gpmc,wr-cycle-ns = <82>;
A Dimx7d-sdb-qspi.dts35 /* take off one dummy cycle */
A Domap3-igep.dtsi129 gpmc,rd-cycle-ns = <82>;
130 gpmc,wr-cycle-ns = <82>;
162 gpmc,rd-cycle-ns = <114>;
163 gpmc,wr-cycle-ns = <114>;
/u-boot/doc/device-tree-bindings/video/
A Dintel-gma.txt15 - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
33 intel,panel-power-cycle-delay = <6>;
/u-boot/board/Seagate/nas220/
A Dkwbimage.cfg36 # bit 4: 0=addr/cmd in smame cycle
116 # bit9 : 0 , no half clock cycle addition to dataout
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/u-boot/doc/device-tree-bindings/memory/
A Dti,gpmc-child.yaml92 # Access time and cycle time timings (in nanoseconds) corresponding to
99 description: Start-cycle to first data valid delay
102 gpmc,rd-cycle-ns:
103 description: Total read cycle time
106 gpmc,wr-cycle-ns:
107 description: Total write cycle time
/u-boot/board/Marvell/dreamplug/
A Dkwbimage.cfg32 # bit 4: 0=addr/cmd in smame cycle
111 # bit9 : 0 , no half clock cycle addition to dataout
112 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
113 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/u-boot/board/Marvell/sheevaplug/
A Dkwbimage.cfg31 # bit 4: 0=addr/cmd in smame cycle
110 # bit9 : 0 , no half clock cycle addition to dataout
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
112 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/u-boot/board/Synology/ds109/
A Dkwbimage.cfg35 # bit 4: 0=addr/cmd in smame cycle
114 # bit9 : 0 , no half clock cycle addition to dataout
115 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
116 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/u-boot/board/cloudengines/pogo_v4/
A Dkwbimage.cfg32 # bit 4: 0=addr/cmd in smame cycle
111 # bit9 : 0 , no half clock cycle addition to dataout
112 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
113 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/u-boot/board/Marvell/guruplug/
A Dkwbimage.cfg31 # bit 4: 0=addr/cmd in smame cycle
110 # bit9 : 0 , no half clock cycle addition to dataout
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
112 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/u-boot/board/Seagate/dockstar/
A Dkwbimage.cfg34 # bit 4: 0=addr/cmd in smame cycle
113 # bit9 : 0 , no half clock cycle addition to dataout
114 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
115 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/u-boot/board/Seagate/goflexhome/
A Dkwbimage.cfg37 # bit 4: 0=addr/cmd in smame cycle
116 # bit9 : 0 , no half clock cycle addition to dataout
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh

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