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Searched refs:dbi_base (Results 1 – 9 of 9) sorted by relevance

/u-boot/drivers/pci/
A Dpcie_imx.c102 void __iomem *dbi_base; member
143 ret = pcie_phy_poll_ack(dbi_base, 1); in pcie_phy_wait_ack()
150 ret = pcie_phy_poll_ack(dbi_base, 0); in pcie_phy_wait_ack()
171 ret = pcie_phy_poll_ack(dbi_base, 1); in pcie_phy_read()
181 ret = pcie_phy_poll_ack(dbi_base, 0); in pcie_phy_read()
206 ret = pcie_phy_poll_ack(dbi_base, 1); in pcie_phy_write()
215 ret = pcie_phy_poll_ack(dbi_base, 0); in pcie_phy_write()
224 ret = pcie_phy_poll_ack(dbi_base, 1); in pcie_phy_write()
233 ret = pcie_phy_poll_ack(dbi_base, 0); in pcie_phy_write()
344 va_address = priv->dbi_base; in get_bus_address()
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A Dpcie_ecam_synquacer.c184 phys_addr_t dbi_base; member
189 .dbi_base = SYNQUACER_PCI_SEG0_DBI_BASE,
193 .dbi_base = SYNQUACER_PCI_SEG1_DBI_BASE,
205 void *dbi_base; member
347 pcie->dbi_base = map_physmem(synquacer_pci_bases[i].dbi_base, in pci_synquacer_ecam_of_to_plat()
349 if (!pcie->dbi_base) { in pci_synquacer_ecam_of_to_plat()
435 dbi_base + IATU_VIEWPORT_OFF); in pcie_sq_prog_outbound_atu()
491 pci_synquacer_dbi_init(pcie->dbi_base); in pci_synquacer_post_init()
493 or_writel(pcie->dbi_base, PCI_COMMAND, in pci_synquacer_post_init()
500 pcie_sq_prog_outbound_atu(pcie->dbi_base, 0, in pci_synquacer_post_init()
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A Dpcie_dw_meson.c115 val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); in meson_pcie_configure()
120 writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); in meson_pcie_configure()
230 val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_payload()
232 writel(val, priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_payload()
234 val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_payload()
236 writel(val, priv->dw.dbi_base + PCI_EXP_DEVCTL); in meson_set_max_payload()
249 val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_rd_req_size()
251 writel(val, priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_rd_req_size()
255 writel(val, priv->dw.dbi_base + PCI_EXP_DEVCTL); in meson_set_max_rd_req_size()
340 priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0); in meson_pcie_parse_dt()
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A Dpcie_uniphier.c83 void *dbi_base; member
118 priv->dbi_base + PCIE_ATU_VIEWPORT); in pcie_dw_prog_outbound_atu()
120 priv->dbi_base + PCIE_ATU_LOWER_BASE); in pcie_dw_prog_outbound_atu()
122 priv->dbi_base + PCIE_ATU_UPPER_BASE); in pcie_dw_prog_outbound_atu()
124 priv->dbi_base + PCIE_ATU_LIMIT); in pcie_dw_prog_outbound_atu()
126 priv->dbi_base + PCIE_ATU_LOWER_TARGET); in pcie_dw_prog_outbound_atu()
128 priv->dbi_base + PCIE_ATU_UPPER_TARGET); in pcie_dw_prog_outbound_atu()
130 writel(type, priv->dbi_base + PCIE_ATU_CR1); in pcie_dw_prog_outbound_atu()
156 *paddr = (void *)(priv->dbi_base + offset); in uniphier_pcie_conf_address()
300 priv->dbi_base = map_physmem(priv->dbi_res.start, in uniphier_pcie_probe()
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A Dpcie_dw_ti.c89 val = readl(pci->dw.dbi_base + PCIE_LINK_CAPABILITY); in pcie_dw_configure()
92 writel(val, pci->dw.dbi_base + PCIE_LINK_CAPABILITY); in pcie_dw_configure()
94 val = readl(pci->dw.dbi_base + PCIE_LINK_CTL_2); in pcie_dw_configure()
97 writel(val, pci->dw.dbi_base + PCIE_LINK_CTL_2); in pcie_dw_configure()
113 val = readl(pci->dw.dbi_base + PCIE_PORT_DEBUG0); in is_link_up()
221 writew(id & PCIE_VENDORID_MASK, pci->dw.dbi_base + PCI_VENDOR_ID); in pcie_dw_init_id()
222 writew(id >> PCIE_DEVICEID_SHIFT, pci->dw.dbi_base + PCI_DEVICE_ID); in pcie_dw_init_id()
320 pcie->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbics"); in pcie_dw_ti_of_to_plat()
321 if ((fdt_addr_t)pcie->dw.dbi_base == FDT_ADDR_T_NONE) in pcie_dw_ti_of_to_plat()
A Dpcie_dw_common.c22 return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) & in pcie_dw_get_link_speed()
28 return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) & in pcie_dw_get_link_width()
128 va_address = (uintptr_t)pcie->dbi_base; in set_cfg_address()
286 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in pcie_dw_setup_host()
290 pci->dbi_base + PCI_BASE_ADDRESS_0); in pcie_dw_setup_host()
291 writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1); in pcie_dw_setup_host()
294 clrsetbits_le32(pci->dbi_base + PCI_INTERRUPT_LINE, in pcie_dw_setup_host()
298 clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS, in pcie_dw_setup_host()
302 clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS, in pcie_dw_setup_host()
310 writew(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE); in pcie_dw_setup_host()
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A Dpcie_dw_sifive.c266 val = readl(sv->dw.dbi_base + PHY_DEBUG_R1); in pcie_sifive_check_link()
282 val = readl(sv->dw.dbi_base + PCIE_MISC_CONTROL_1); in pcie_sifive_force_gen1()
284 writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1); in pcie_sifive_force_gen1()
287 linkcap = readl(sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP); in pcie_sifive_force_gen1()
289 writel(linkcap, sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP); in pcie_sifive_force_gen1()
293 writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1); in pcie_sifive_force_gen1()
299 readl(sv->dw.dbi_base + PHY_DEBUG_R0), in pcie_sifive_print_phy_debug()
300 readl(sv->dw.dbi_base + PHY_DEBUG_R1)); in pcie_sifive_print_phy_debug()
316 val = readl(sv->dw.dbi_base + PHY_DEBUG_R1); in pcie_sifive_wait_for_link()
449 sv->dw.dbi_base = get_fdt_addr(dev, "dbi"); in pcie_sifive_of_to_plat()
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A Dpcie_dw_common.h116 void __iomem *dbi_base; member
146 val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF); in dw_pcie_dbi_write_enable()
151 writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF); in dw_pcie_dbi_write_enable()
A Dpcie_dw_rockchip.c164 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY, in rk_pcie_configure()
167 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2, in rk_pcie_configure()
357 priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0); in rockchip_pcie_parse_dt()
358 if (!priv->dw.dbi_base) in rockchip_pcie_parse_dt()
361 dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base); in rockchip_pcie_parse_dt()

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