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Searched refs:ddr (Results 1 – 25 of 328) sorted by relevance

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/u-boot/drivers/ddr/fsl/
A Dfsl_ddr_gen4.c58 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
126 ddr_out32(&ddr->cs0_bnds, in fsl_ddr_set_memctl_regs()
128 ddr_out32(&ddr->cs0_config, in fsl_ddr_set_memctl_regs()
139 ddr_out32(&ddr->cs1_bnds, in fsl_ddr_set_memctl_regs()
149 ddr_out32(&ddr->cs2_bnds, in fsl_ddr_set_memctl_regs()
159 ddr_out32(&ddr->cs3_bnds, in fsl_ddr_set_memctl_regs()
231 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
237 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
274 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
285 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen3.c30 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
163 out_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
169 out_be32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
219 out_be32(&ddr->mtcr, 0); in fsl_ddr_set_memctl_regs()
233 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
244 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
253 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
264 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
420 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
506 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
[all …]
A Darm_ddr_gen3.c36 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
43 ddr = (void *)CFG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
47 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
52 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
57 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
69 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
128 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
131 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
137 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
145 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
[all …]
A Dctrl_regs.c227 ddr->cs[i].config = (0 in set_csn_config()
440 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
493 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
621 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
714 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
850 ddr->ddr_sdram_cfg = (0 in set_ddr_sdram_cfg()
1914 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1944 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1962 ddr->timing_cfg_6 = (0 in set_timing_cfg_6()
2191 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
[all …]
A Dmpc85xx_ddr_gen2.c20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
50 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
51 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
55 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
58 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
59 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
78 out_be32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
88 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen1.c20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
31 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
59 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); in fsl_ddr_set_memctl_regs()
73 struct ccsr_ddr __iomem *ddr = in ddr_enable_ecc() local
[all …]
A Dutil.c32 struct ccsr_ddr __iomem *ddr; in fsl_ddr_get_version() local
37 ddr = (void *)CFG_SYS_FSL_DDR_ADDR; in fsl_ddr_get_version()
41 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; in fsl_ddr_get_version()
46 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; in fsl_ddr_get_version()
51 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_get_version()
183 struct ccsr_ddr __iomem *ddr = in print_ddr_info() local
351 struct ccsr_ddr __iomem *ddr; in fsl_ddr_sync_memctl_refresh() local
356 ddr = (void *)CFG_SYS_FSL_DDR_ADDR; in fsl_ddr_sync_memctl_refresh()
360 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; in fsl_ddr_sync_memctl_refresh()
365 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; in fsl_ddr_sync_memctl_refresh()
[all …]
/u-boot/post/cpu/mpc83xx/
A Decc.c29 __raw_writel(0, &ddr->capture_address); in ecc_clear()
30 __raw_writel(0, &ddr->capture_data_hi); in ecc_clear()
31 __raw_writel(0, &ddr->capture_data_lo); in ecc_clear()
32 __raw_writel(0, &ddr->capture_ecc); in ecc_clear()
33 __raw_writel(0, &ddr->capture_attributes); in ecc_clear()
53 ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; in ecc_post_test() local
78 ecc_clear(ddr); in ecc_post_test()
118 ddr->data_err_inject_hi, in ecc_post_test()
119 ddr->data_err_inject_lo, in ecc_post_test()
125 ddr->capture_data_hi, ddr->capture_data_lo); in ecc_post_test()
[all …]
/u-boot/arch/powerpc/cpu/mpc83xx/
A Decc.c18 struct ccsr_ddr __iomem *ddr = &immap->ddr; in ecc_print_status() local
20 ddr83xx_t *ddr = &immap->ddr; in ecc_print_status() local
46 ddr->data_err_inject_hi, ddr->data_err_inject_lo); in ecc_print_status()
77 ddr->capture_data_hi, ddr->capture_data_lo); in ecc_print_status()
102 struct ccsr_ddr __iomem *ddr = &immap->ddr; in do_ecc() local
104 ddr83xx_t *ddr = &immap->ddr; in do_ecc() local
133 ddr->capture_ecc = 0; in do_ecc()
150 ddr->err_sbe = val; in do_ecc()
163 ddr->err_sbe = val; in do_ecc()
198 val = ddr->err_detect; in do_ecc()
[all …]
A Dspd_sdram.c35 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info() local
134 volatile ddr83xx_t *ddr = &immap->ddr; in spd_sdram() local
242 ddr->cs_config[1] = ( 1<<31 in spd_sdram()
267 ddr->cs_config[3] = ( 1<<31 in spd_sdram()
475 ddr->timing_cfg_0 = (0 in spd_sdram()
538 ddr->timing_cfg_1 = in spd_sdram()
630 ddr->timing_cfg_2 = (0 in spd_sdram()
693 ddr->sdram_mode = in spd_sdram()
711 ddr->sdram_mode2 = 0; in spd_sdram()
761 ddr->sdram_cfg2 = (0 in spd_sdram()
[all …]
/u-boot/board/freescale/ls1021atsn/
A Dls1021atsn.c34 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
36 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
37 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
48 out_be32(&ddr->sdram_cfg_2, in ddrmc_init()
51 out_be32(&ddr->init_ext_addr, (1 << 31)); in ddrmc_init()
54 out_be32(&ddr->ddr_cdr2, in ddrmc_init()
60 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
63 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
73 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
81 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
[all …]
/u-boot/board/freescale/ls1021aiot/
A Dls1021aiot.c57 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
59 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
60 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
62 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
69 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); in ddrmc_init()
70 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
72 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
82 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
85 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); in ddrmc_init()
90 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
[all …]
/u-boot/board/socrates/
A Dsdram.c28 struct ccsr_ddr __iomem *ddr = in fixed_sdram() local
34 ddr->cs0_config = 0; in fixed_sdram()
35 ddr->sdram_cfg = 0; in fixed_sdram()
37 ddr->cs0_bnds = CFG_SYS_DDR_CS0_BNDS; in fixed_sdram()
38 ddr->cs0_config = CFG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
39 ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0; in fixed_sdram()
40 ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1; in fixed_sdram()
41 ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2; in fixed_sdram()
42 ddr->sdram_mode = CFG_SYS_DDR_MODE; in fixed_sdram()
44 ddr->sdram_cfg_2 = CFG_SYS_DDR_CONFIG_2; in fixed_sdram()
[all …]
/u-boot/board/gdsys/mpc8308/
A Dsdram.c45 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
49 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
52 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in fixed_sdram()
53 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); in fixed_sdram()
54 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in fixed_sdram()
55 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in fixed_sdram()
57 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
58 out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
59 out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); in fixed_sdram()
60 out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); in fixed_sdram()
[all …]
/u-boot/board/freescale/ls1021atwr/
A Dls1021atwr.c149 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
151 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
152 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
163 out_be32(&ddr->sdram_cfg_2, in ddrmc_init()
166 out_be32(&ddr->init_ext_addr, (1 << 31)); in ddrmc_init()
169 out_be32(&ddr->ddr_cdr2, in ddrmc_init()
175 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
178 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
188 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
196 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
[all …]
/u-boot/arch/arm/mach-imx/mx6/
A Dddr.c753 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6sl_dram_iocfg()
754 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6sl_dram_iocfg()
780 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6sl_dram_iocfg()
781 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6sl_dram_iocfg()
810 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6dq_dram_iocfg()
811 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6dq_dram_iocfg()
852 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6dq_dram_iocfg()
853 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6dq_dram_iocfg()
888 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6sdl_dram_iocfg()
889 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6sdl_dram_iocfg()
[all …]
/u-boot/board/freescale/mpc837xerdb/
A Dmpc837xerdb.c113 im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
116 im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0; in fixed_sdram()
117 im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1; in fixed_sdram()
118 im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2; in fixed_sdram()
119 im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3; in fixed_sdram()
120 im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
121 im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2; in fixed_sdram()
122 im->ddr.sdram_mode = CFG_SYS_DDR_MODE; in fixed_sdram()
123 im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2; in fixed_sdram()
124 im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL; in fixed_sdram()
[all …]
/u-boot/board/keymile/km83xx/
A Dkm83xx.c215 out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
216 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in fixed_sdram()
217 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); in fixed_sdram()
218 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in fixed_sdram()
219 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in fixed_sdram()
220 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
221 out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
222 out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); in fixed_sdram()
223 out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); in fixed_sdram()
227 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
[all …]
/u-boot/drivers/ddr/imx/
A DKconfig1 source "drivers/ddr/imx/imx8m/Kconfig"
2 source "drivers/ddr/imx/imx8ulp/Kconfig"
3 source "drivers/ddr/imx/imx9/Kconfig"
4 source "drivers/ddr/imx/phy/Kconfig"
/u-boot/arch/arm/dts/
A Dimx8mq-cm-u-boot.dtsi21 u-boot-spl-ddr {
22 filename = "u-boot-spl-ddr.bin";
31 ddr-1d-imem-fw {
37 ddr-1d-dmem-fw {
43 ddr-2d-imem-fw {
49 ddr-2d-dmem-fw {
61 filename = "u-boot-spl-ddr.bin";
A Dimx8mq-u-boot.dtsi38 u-boot-spl-ddr {
41 filename = "u-boot-spl-ddr.bin";
49 ddr-1d-imem-fw {
55 ddr-1d-dmem-fw {
61 ddr-2d-imem-fw {
67 ddr-2d-dmem-fw {
90 filename = "u-boot-spl-ddr.bin";
A Dimx8mp-u-boot.dtsi54 u-boot-spl-ddr {
55 filename = "u-boot-spl-ddr.bin";
64 ddr-1d-imem-fw {
70 ddr-1d-dmem-fw {
76 ddr-2d-imem-fw {
82 ddr-2d-dmem-fw {
96 filename = "u-boot-spl-ddr.bin";
/u-boot/drivers/
A DMakefile48 obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR) += ddr/fsl/
49 obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
50 obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
51 obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
52 obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
53 obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
54 obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/
73 obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR) += ddr/fsl/
122 obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
/u-boot/board/cssi/cmpcpro/
A Dcmpcpro.c305 out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL); in dram_init()
307 out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); in dram_init()
309 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in dram_init()
310 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); in dram_init()
311 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in dram_init()
312 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in dram_init()
313 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); in dram_init()
314 out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); in dram_init()
315 out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); in dram_init()
316 out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); in dram_init()
[all …]
/u-boot/arch/mips/dts/
A Dmt7621-u-boot.dtsi49 u-boot-spl-ddr {
52 filename = "u-boot-spl-ddr.bin";
67 filename = "u-boot-spl-ddr.img";
82 filename = "u-boot-spl-ddr.bin";
102 filename = "u-boot-spl-ddr.img";

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