| /u-boot/drivers/video/rockchip/ |
| A D | rk_mipi.c | 205 u64 ddr_clk = priv->phy_clk; in rk_mipi_phy_enable() local
232 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; in rk_mipi_phy_enable()
243 if (ddr_clk / (MHz) <= freq_rang[i][0]) in rk_mipi_phy_enable()
273 if ((ddr_clk * i % refclk < remain) && in rk_mipi_phy_enable()
274 (ddr_clk * i / refclk) < max_fbdiv) { in rk_mipi_phy_enable()
276 remain = ddr_clk * i % refclk; in rk_mipi_phy_enable()
279 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
280 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
281 priv->phy_clk = ddr_clk; in rk_mipi_phy_enable()
284 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
|
| /u-boot/drivers/clk/mtmips/ |
| A D | clk-mt7621.c | 50 int ddr_clk; member
125 return priv->ddr_clk; in mt7621_clk_get_rate()
194 u32 xtal_clk, xtal_div, ffiv, ffrac, cpu_clk, ddr_clk; in mt7621_get_clocks() local
233 ddr_clk = fb * xtal_clk / xtal_div; in mt7621_get_clocks()
237 ddr_clk *= 2; in mt7621_get_clocks()
241 priv->ddr_clk = ddr_clk; in mt7621_get_clocks()
|
| /u-boot/arch/mips/mach-mtmips/mt7621/ |
| A D | init.c | 32 u32 cpu_clk, ddr_clk, bus_clk, xtal_clk; in print_cpuinfo() local
71 ddr_clk = clk_get_rate(&clk); in print_cpuinfo()
81 cpu_clk / 1000000, ddr_clk / 500000, bus_clk / 1000000, in print_cpuinfo()
|
| /u-boot/drivers/ram/sifive/ |
| A D | sifive_ddr.c | 91 struct clk ddr_clk; member
348 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in sifive_ddr_probe()
359 ret = clk_set_rate(&priv->ddr_clk, clock); in sifive_ddr_probe()
366 ret = clk_enable(&priv->ddr_clk); in sifive_ddr_probe()
|
| /u-boot/drivers/ram/k3-ddrss/ |
| A D | k3-ddrss.c | 135 struct clk ddr_clk; member
223 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); in k3_lpddr4_freq_update()
225 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2); in k3_lpddr4_freq_update()
227 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0); in k3_lpddr4_freq_update()
275 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); in k3_ddrss_init_freq()
278 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0); in k3_ddrss_init_freq()
376 ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk); in k3_ddrss_ofdata_to_priv()
|
| /u-boot/arch/arm/mach-omap2/ |
| A D | clocks-common.c | 272 u32 ddr_clk, sys_clk_khz, omap_rev, divider; in omap_ddr_clk() local
283 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / in omap_ddr_clk()
300 ddr_clk = ddr_clk / divider / core_dpll_params->m2; in omap_ddr_clk()
301 ddr_clk *= 1000; /* convert to Hz */ in omap_ddr_clk()
302 debug("ddr_clk %d\n ", ddr_clk); in omap_ddr_clk()
304 return ddr_clk; in omap_ddr_clk()
|
| /u-boot/drivers/ram/stm32mp1/ |
| A D | stm32mp1_ram.c | 37 unsigned long ddr_clk; in stm32mp1_ddr_clk_enable() local
60 ddr_clk = abs(ddrphy_clk - mem_speed * 1000); in stm32mp1_ddr_clk_enable()
61 if (ddr_clk > (mem_speed * 100)) { in stm32mp1_ddr_clk_enable()
|
| /u-boot/drivers/ram/aspeed/ |
| A D | sdram_ast2500.c | 70 struct clk ddr_clk; member
336 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in ast2500_sdrammc_probe()
349 clk_set_rate(&priv->ddr_clk, priv->clock_rate); in ast2500_sdrammc_probe()
|
| A D | sdram_ast2600.c | 545 struct clk ddr_clk; member
|
| /u-boot/drivers/ram/rockchip/ |
| A D | sdram_rk322x.c | 37 struct clk ddr_clk; member
692 ret = clk_set_rate(&dram->ddr_clk, in sdram_init()
804 priv->ddr_clk.id = CLK_DDR; in rk322x_dmc_probe()
805 ret = clk_request(dev_clk, &priv->ddr_clk); in rk322x_dmc_probe()
|
| A D | sdram_rk3066.c | 41 struct clk ddr_clk; member
697 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in rk3066_dmc_sdram_init()
844 priv->ddr_clk.id = CLK_DDR; in rk3066_dmc_probe()
845 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3066_dmc_probe()
|
| A D | dmc-rk3368.c | 29 struct clk ddr_clk; member
812 ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq); in setup_sdram()
948 priv->ddr_clk.id = CLK_DDR; in rk3368_dmc_probe()
949 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3368_dmc_probe()
|
| A D | sdram_rk3188.c | 40 struct clk ddr_clk; member
726 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
910 priv->ddr_clk.id = CLK_DDR; in rk3188_dmc_probe()
911 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3188_dmc_probe()
|
| A D | sdram_rk3288.c | 42 struct clk ddr_clk; member
802 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
1078 priv->ddr_clk.id = CLK_DDR; in rk3288_dmc_probe()
1079 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3288_dmc_probe()
|
| A D | sdram_rk3399.c | 71 struct clk ddr_clk; member
2505 ret_clk = clk_set_rate(&dram->ddr_clk, hz); in lpddr4_set_ctl()
3119 ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->ddr_clk); in rk3399_dmc_init()
3121 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in rk3399_dmc_init()
3128 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); in rk3399_dmc_init()
|
| A D | sdram_rk3328.c | 28 struct clk ddr_clk; member
|
| /u-boot/arch/arm/dts/ |
| A D | imx7ulp.dtsi | 281 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
313 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
|
| /u-boot/drivers/ddr/altera/ |
| A D | sdram_n5x.c | 1195 struct clk *ddr_clk; in enable_ddr_clock() local
1199 ddr_clk = devm_clk_get(dev, "mem_clk"); in enable_ddr_clock()
1200 if (!IS_ERR(ddr_clk)) { in enable_ddr_clock()
1201 ret = clk_enable(ddr_clk); in enable_ddr_clock()
1207 ret = PTR_ERR(ddr_clk); in enable_ddr_clock()
|