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Searched refs:ddr_ddrphy_cfg (Results 1 – 25 of 42) sorted by relevance

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/u-boot/board/freescale/imx93_evk/
A Dlpddr4x_timing_ld.c53 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1487 .ddrphy_cfg = ddr_ddrphy_cfg,
1488 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/bsh/imx8mn_smm_s2/
A Dddr3l_timing_256m.c90 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
932 .ddrphy_cfg = ddr_ddrphy_cfg,
933 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dddr3l_timing_512m.c90 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
932 .ddrphy_cfg = ddr_ddrphy_cfg,
933 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/variscite/imx8mn_var_som/
A Dddr4_timing.c113 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
521 .ddrphy_cfg = ddr_ddrphy_cfg,
522 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/google/imx8mq_phanbell/
A Dlpddr4_timing_1g.c104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1722 .ddrphy_cfg = ddr_ddrphy_cfg,
1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/kontron/sl-mx8mm/
A Dlpddr4_timing.c96 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1706 .ddrphy_cfg = ddr_ddrphy_cfg,
1707 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/freescale/imx8mn_evk/
A Dddr4_timing.c110 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1045 .ddrphy_cfg = ddr_ddrphy_cfg,
1046 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dddr4_timing_ld.c114 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1047 .ddrphy_cfg = ddr_ddrphy_cfg,
1048 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dlpddr4_timing.c124 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1578 .ddrphy_cfg = ddr_ddrphy_cfg,
1579 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/technexion/pico-imx8mq/
A Dlpddr4_timing_1gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dlpddr4_timing_2gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dlpddr4_timing_3gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dlpddr4_timing_4gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/gateworks/venice/
A Dlpddr4_timing_imx8mm_512mb.c127 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1840 .ddrphy_cfg = ddr_ddrphy_cfg,
1841 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/phytec/phycore_imx8mm/
A Dlpddr4_timing.c121 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1837 .ddrphy_cfg = ddr_ddrphy_cfg,
1838 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/
A Dlpddr4_timing_01061010.1_2.c122 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1838 .ddrphy_cfg = ddr_ddrphy_cfg,
1839 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dlpddr4_timing_01061010.c122 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1838 .ddrphy_cfg = ddr_ddrphy_cfg,
1839 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dlpddr4_timing_ff000110.c122 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1838 .ddrphy_cfg = ddr_ddrphy_cfg,
1839 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dlpddr4_timing_ff020008.c122 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1838 .ddrphy_cfg = ddr_ddrphy_cfg,
1839 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/data_modul/imx8mm_edm_sbc/
A Dlpddr4_timing_2G_32.c124 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1837 .ddrphy_cfg = ddr_ddrphy_cfg,
1838 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dlpddr4_timing_4G_32.c124 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1837 .ddrphy_cfg = ddr_ddrphy_cfg,
1838 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/data_modul/imx8mp_edm_sbc/
A Dlpddr4_timing_4G_32.c130 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1840 .ddrphy_cfg = ddr_ddrphy_cfg,
1841 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c127 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1839 .ddrphy_cfg = ddr_ddrphy_cfg,
1840 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/u-boot/board/dhelectronics/dh_imx8mp/
A Dlpddr4_timing_2G_32.c126 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1836 .ddrphy_cfg = ddr_ddrphy_cfg,
1837 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
A Dlpddr4_timing_4G_32.c125 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1835 .ddrphy_cfg = ddr_ddrphy_cfg,
1836 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),

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