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Searched refs:ddr_ddrphy_trained_csr (Results 1 – 25 of 44) sorted by relevance

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/u-boot/board/gateworks/venice/
A Dlpddr4_timing_imx8mn.c10 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1435 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1436 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1900 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1901 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
2364 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
2365 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing_imx8mm_512mb.c331 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1844 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1845 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing_imx8mp.c10 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1841 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1842 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/freescale/imx93_evk/
A Dlpddr4x_timing_ld.c126 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1491 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1492 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/bsh/imx8mn_smm_s2/
A Dddr3l_timing_256m.c184 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
936 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
937 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dddr3l_timing_512m.c184 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
936 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
937 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/google/imx8mq_phanbell/
A Dlpddr4_timing_1g.c269 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1726 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1727 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/kontron/sl-mx8mm/
A Dlpddr4_timing.c255 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1710 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1711 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/freescale/imx8mn_evk/
A Dddr4_timing.c214 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1049 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1050 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dddr4_timing_ld.c218 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1051 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1052 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing.c279 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1582 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1583 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/technexion/pico-imx8mq/
A Dlpddr4_timing_1gb.c271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1728 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1729 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing_2gb.c271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1728 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1729 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing_3gb.c271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1728 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1729 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing_4gb.c271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1728 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1729 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/phytec/phycore_imx8mm/
A Dlpddr4_timing.c325 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1841 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1842 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/
A Dlpddr4_timing_01061010.1_2.c326 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1842 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1843 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing_01061010.c326 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1842 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1843 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing_ff000110.c326 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1842 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1843 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing_ff020008.c326 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1842 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1843 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/data_modul/imx8mm_edm_sbc/
A Dlpddr4_timing_2G_32.c328 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1841 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1842 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
A Dlpddr4_timing_4G_32.c328 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1841 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1842 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/data_modul/imx8mp_edm_sbc/
A Dlpddr4_timing_4G_32.c339 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1844 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1845 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c331 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1843 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1844 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
/u-boot/board/dhelectronics/dh_imx8mp/
A Dlpddr4_timing_2G_32.c335 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { variable
1840 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1841 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),

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