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Searched refs:ddr_sdram_cfg_2 (Results 1 – 10 of 10) sorted by relevance

/u-boot/drivers/ddr/fsl/
A Dmpc85xx_ddr_gen3.c164 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
174 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
218 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); in fsl_ddr_set_memctl_regs()
343 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
539 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); in fsl_ddr_set_memctl_regs()
557 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
A Dfsl_ddr_gen4.c232 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
242 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
250 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { in fsl_ddr_set_memctl_regs()
296 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
428 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { in fsl_ddr_set_memctl_regs()
448 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
A Darm_ddr_gen3.c132 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
142 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
A Dmpc85xx_ddr_gen2.c71 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
A Dctrl_regs.c952 ddr->ddr_sdram_cfg_2 = (0 in set_ddr_sdram_cfg_2()
971 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); in set_ddr_sdram_cfg_2()
1190 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && in set_ddr_sdram_mode_9()
1225 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && in set_ddr_sdram_mode_9()
1985 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN && in set_timing_cfg_7()
A Dinteractive.c637 CFG_REGS(ddr_sdram_cfg_2), in print_fsl_memctl_config_regs()
728 CFG_REGS(ddr_sdram_cfg_2), in fsl_ddr_regs_edit()
/u-boot/board/freescale/ls1043ardb/
A Dddr.h64 .ddr_sdram_cfg_2 = 0x00401100,
/u-boot/board/kontron/sl28/
A Dddr.c32 .ddr_sdram_cfg_2 = 0x24401111,
/u-boot/board/freescale/p1_p2_rdb_pc/
A Dddr.c225 .ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2, in fixed_sdram()
/u-boot/include/
A Dfsl_ddr_sdram.h253 unsigned int ddr_sdram_cfg_2; member

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