| /u-boot/board/technexion/pico-imx8mq/ |
| A D | pico-imx8mq.c | 57 int ddr_size = readl(M4_BOOTROM_BASE_ADDR); in board_phys_sdram_size() local
59 if (ddr_size == 0x4) { in board_phys_sdram_size()
61 } else if (ddr_size == 0x3) { in board_phys_sdram_size()
63 } else if (ddr_size == 0x2) { in board_phys_sdram_size()
65 } else if (ddr_size == 0x1) { in board_phys_sdram_size()
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| /u-boot/board/kontron/sl-mx8mm/ |
| A D | sl-mx8mm.c | 40 u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR); in board_phys_sdram_size() local
42 if (ddr_size == 4) { in board_phys_sdram_size()
44 } else if (ddr_size == 3) { in board_phys_sdram_size()
46 } else if (ddr_size == 2) { in board_phys_sdram_size()
48 } else if (ddr_size == 1) { in board_phys_sdram_size()
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| /u-boot/board/cortina/presidio-asic/ |
| A D | presidio.c | 111 unsigned int ddr_size; in dram_init() local
113 ddr_size = readl(0x111100c); in dram_init()
114 gd->ram_size = ddr_size * 0x100000; in dram_init()
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| /u-boot/drivers/ram/renesas/rzn1/ |
| A D | ddr_async.c | 35 u32 ddr_size; member
217 priv->ddr_size = priv->ddr_size / 2; in rzn1_dram_init()
222 ddr_start_addr, priv->ddr_size, in rzn1_dram_init()
240 memset((void *)RZN1_V_DDR_BASE, 0xff, priv->ddr_size); in rzn1_dram_init()
326 ret = ofnode_read_u32(subnode, "size", &priv->ddr_size); in cadence_ddr_probe()
347 if (cadence_ddr_test((long *)RZN1_V_DDR_BASE, priv->ddr_size)) { in cadence_ddr_probe()
349 gd->ram_size = priv->ddr_size; in cadence_ddr_probe()
354 if (!priv->ddr_size) in cadence_ddr_probe()
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| /u-boot/board/keymile/km83xx/ |
| A D | km83xx.c | 210 u32 ddr_size; in fixed_sdram() local
234 for (ddr_size = msize << 20, ddr_size_log2 = 0; in fixed_sdram()
235 (ddr_size > 1); in fixed_sdram()
236 ddr_size = ddr_size >> 1, ddr_size_log2++) in fixed_sdram()
237 if (ddr_size & 1) in fixed_sdram()
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | ddr.c | 210 size_t ddr_size; in fixed_sdram() local
247 ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; in fixed_sdram()
252 ddr_size, LAW_TRGT_IF_DDR_1) < 0) { in fixed_sdram()
257 return ddr_size; in fixed_sdram()
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| /u-boot/drivers/ram/stm32mp1/ |
| A D | stm32mp1_ram.c | 330 u32 ddr_size; in stm32mp1_ddr_size() local
345 ddr_size = (nb_bytes >> data_bus_width) << nb_bit; in stm32mp1_ddr_size()
346 if (ddr_size > STM32_DDR_SIZE) { in stm32mp1_ddr_size()
347 ddr_size = STM32_DDR_SIZE; in stm32mp1_ddr_size()
348 debug("invalid DDR configuration: size = %x\n", ddr_size); in stm32mp1_ddr_size()
351 return ddr_size; in stm32mp1_ddr_size()
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| /u-boot/drivers/ram/sifive/ |
| A D | sifive_ddr.c | 238 const u64 ddr_size = priv->info.size; in sifive_ddr_setup() local
239 const u64 ddr_end = priv->info.base + ddr_size; in sifive_ddr_setup()
317 ddr_size); in sifive_ddr_setup()
322 if (priv->info.size != ddr_size) { in sifive_ddr_setup()
324 (uintptr_t)priv->info.size, (uintptr_t)ddr_size); in sifive_ddr_setup()
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| /u-boot/board/freescale/ls1043ardb/ |
| A D | ddr.c | 181 phys_size_t ddr_size; in fixed_sdram() local
204 ddr_size = (phys_size_t)2048 * 1024 * 1024; in fixed_sdram()
207 return ddr_size; in fixed_sdram()
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| /u-boot/board/variscite/dart_6ul/ |
| A D | dart_6ul.c | 177 u8 ddr_size; member
257 DART6UL_DDRSIZE(info->ddr_size) / SZ_1M, in checkboard()
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| /u-boot/drivers/ram/cadence/ |
| A D | ddr_ctrl.c | 305 u32 ddr_start_addr, u32 ddr_size, in cdns_ddr_ctrl_init() argument
368 ddr_start_addr + ddr_size, 0); in cdns_ddr_ctrl_init()
389 ddr_start_addr, ddr_size); in cdns_ddr_ctrl_init()
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| /u-boot/include/renesas/ |
| A D | ddr_ctrl.h | 44 u32 ddr_start_addr, u32 ddr_size,
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| /u-boot/board/freescale/lx2160a/ |
| A D | lx2160a.c | 550 u64 ddr_size = 0; in detail_board_ddr_info() local
554 ddr_size += gd->bd->bi_dram[i].size; in detail_board_ddr_info()
555 print_size(ddr_size, ""); in detail_board_ddr_info()
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