| /u-boot/arch/arm/mach-stm32mp/include/mach/ |
| A D | ddr.h | 10 enum ddr_type { enum
18 int board_ddr_power_init(enum ddr_type ddr_type);
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| /u-boot/drivers/ddr/marvell/a38x/ |
| A D | ddr3_init.c | 10 static char *ddr_type = "DDR4"; variable
12 static char *ddr_type = "DDR3"; variable
41 mv_ddr_pre_training_soc_config(ddr_type); in ddr3_init()
87 printf("%s Training Sequence - FAILED\n", ddr_type); in ddr3_init()
93 mv_ddr_post_training_soc_config(ddr_type); in ddr3_init()
168 printf("%s Training Sequence - FAILED\n", ddr_type); in mv_ddr_training_params_set()
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| A D | mv_ddr_plat.h | 238 int mv_ddr_pre_training_soc_config(const char *ddr_type);
239 int mv_ddr_post_training_soc_config(const char *ddr_type);
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| /u-boot/arch/mips/mach-mtmips/mt7628/ |
| A D | ddr.c | 75 static void mt7628_ddr_pad_ldo_config(int ddr_type, int pkg_type) in mt7628_ddr_pad_ldo_config() argument
82 if (ddr_type == DRAM_DDR1) in mt7628_ddr_pad_ldo_config()
117 if (ddr_type == DRAM_DDR1) in mt7628_ddr_pad_ldo_config()
134 int ddr_type, pkg_type, lspd; in mt7628_ddr_init() local
138 ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE; in mt7628_ddr_init()
144 ddr_type = DRAM_DDR1; in mt7628_ddr_init()
149 mt7628_ddr_pad_ldo_config(ddr_type, pkg_type); in mt7628_ddr_init()
158 if (ddr_type == DRAM_DDR1) { in mt7628_ddr_init()
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| /u-boot/arch/mips/mach-mtmips/mt7620/ |
| A D | dram.c | 71 int ddr_type, aux; in mt7620_dram_init() local
75 ddr_type = (readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE_M) in mt7620_dram_init()
93 if (ddr_type == DRAM_DDR1) { in mt7620_dram_init()
100 } else if (ddr_type == DRAM_DDR2) { in mt7620_dram_init()
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| /u-boot/drivers/ram/octeon/ |
| A D | dimm_spd_eeprom.c | 293 int ddr_type) in get_dimm_ecc() argument
295 return !!(read_spd(dimm_config, upper_dimm, BUS_WIDTH(ddr_type)) & 8); in get_dimm_ecc()
299 int ddr_type) in get_dimm_module_type() argument
327 int dimm, const char **dimm_types, int ddr_type, in report_common_dimm() argument
336 ddr_type); in report_common_dimm()
337 spd_ecc = get_dimm_ecc(dimm_config, upper_dimm, ddr_type); in report_common_dimm()
341 if_num, dimm, ddr_type, dimm_types[spd_module_type], in report_common_dimm()
398 int ddr_type; in report_dimm() local
401 ddr_type = get_ddr_type(dimm_config, upper_dimm); in report_dimm()
403 if (ddr_type == DDR4_DRAM) in report_dimm()
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| A D | octeon_ddr.c | 156 int ddr_type; in octeon3_refclock() local
180 ddr_type = get_ddr_type(dimm_config, 0); in octeon3_refclock()
181 spd_dimm_type = get_dimm_module_type(dimm_config, 0, ddr_type); in octeon3_refclock()
183 debug("ddr type: 0x%x, dimm type: 0x%x\n", ddr_type, in octeon3_refclock()
186 if (ddr_type == DDR4_DRAM && in octeon3_refclock()
433 int ddr_type; in initialize_ddr_clock() local
437 ddr_type = (read_spd(&dimm_config_table[0], 0, in initialize_ddr_clock()
641 ((ddr_type == DDR4_DRAM) && in initialize_ddr_clock()
950 (ddr_type == DDR4_DRAM) ? 1 : 0; in initialize_ddr_clock()
1566 int ddr_type) in validate_ddr3_rlevel_bitmask() argument
[all …]
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| A D | octeon3_lmc.c | 2654 static enum ddr_type ddr_type __section(".data");
2931 if (ddr_type == DDR4_DRAM) { in lmc_timing_params0()
3005 if (ddr_type == DDR4_DRAM) { in lmc_timing_params1()
3078 if (ddr_type == DDR4_DRAM) { in lmc_timing_params2()
3131 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params0()
3178 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params0()
3205 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params0()
3475 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params2()
3534 if (ddr_type == DDR4_DRAM) { in lmc_modereg_params3()
6623 ddr_type); in rodt_loop()
[all …]
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| /u-boot/board/st/common/ |
| A D | stpmic1.c | 18 int board_ddr_power_init(enum ddr_type ddr_type) in board_ddr_power_init() argument
31 switch (ddr_type) { in board_ddr_power_init()
117 switch (ddr_type) { in board_ddr_power_init()
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| /u-boot/drivers/ddr/imx/imx8m/ |
| A D | ddr_init.c | 164 unsigned int i, ddr_type, tmp; in get_trained_CDD() local
169 ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; in get_trained_CDD()
170 if (ddr_type == 0x20) { in get_trained_CDD()
223 unsigned int i, ddr_type; in update_umctl2_rank_space_setting() local
227 ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; in update_umctl2_rank_space_setting()
230 if (ddr_type == 0x20) { in update_umctl2_rank_space_setting()
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| /u-boot/board/rockchip/evb_rk3036/ |
| A D | evb_rk3036.c | 15 config->ddr_type = 3; in get_ddr_config()
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| /u-boot/board/rockchip/kylin_rk3036/ |
| A D | kylin_rk3036.c | 18 config->ddr_type = 3; in get_ddr_config()
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| /u-boot/drivers/ram/renesas/rzn1/ |
| A D | ddr_async.c | 87 static void ddr_phy_init(struct cadence_ddr_info *priv, int ddr_type) in ddr_phy_init() argument
111 if (ddr_type == RZN1_DDR3_DUAL_BANK) in ddr_phy_init()
113 else if (ddr_type == RZN1_DDR3_SINGLE_BANK) in ddr_phy_init()
120 if (ddr_type == RZN1_DDR3_DUAL_BANK) in ddr_phy_init()
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| /u-boot/drivers/ddr/altera/ |
| A D | sdram_n5x.c | 325 enum ddr_type { enum
348 enum ddr_type cntlr_t;
355 enum ddr_type cntlr2_t;
527 enum ddr_type umctl2_type) in enable_quasi_dynamic_reg_grp3()
648 enum ddr_type umctl2_type) in scrubber_ddr_config()
875 enum ddr_type umctl2_type) in phy_pre_handoff_config()
1218 enum ddr_type umctl2_type) in ddr_start_dfi_init()
1252 enum ddr_type umctl2_type) in ddr_check_dfi_init_complete()
1300 enum ddr_type umctl2_type) in ddr_trigger_sdram_init()
1337 enum ddr_type umctl2_type) in ddr_post_handoff_config()
[all …]
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| /u-boot/arch/x86/include/asm/ |
| A D | global_data.h | 24 uint16_t ddr_type; member
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| /u-boot/arch/x86/include/asm/arch-quark/ |
| A D | mrc.h | 114 uint8_t ddr_type; /* DDR3, DDR3L */ member
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| /u-boot/board/engicam/common/ |
| A D | spl.c | 223 .ddr_type = DDR_TYPE_DDR3,
335 .ddr_type = DDR_TYPE_DDR3,
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| /u-boot/board/freescale/mx6ul_14x14_evk/ |
| A D | mx6ul_14x14_evk.c | 419 .ddr_type = DDR_TYPE_LPDDR2,
459 .ddr_type = DDR_TYPE_DDR3,
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| /u-boot/drivers/ram/ |
| A D | mpc83xx_sdram.c | 316 u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr; in mpc83xx_sdram_probe() local
408 ddr_type = dev_read_u32_default(dev, "ddr_type", 0); in mpc83xx_sdram_probe()
409 if (ddr_type > 1) { in mpc83xx_sdram_probe()
411 dev->name, ddr_type); in mpc83xx_sdram_probe()
433 ddr_type << (31 - 13) | in mpc83xx_sdram_probe()
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| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | litesom.c | 132 .ddr_type = DDR_TYPE_DDR3,
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| A D | opos6ul.c | 132 .ddr_type = DDR_TYPE_DDR3,
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| /u-boot/arch/mips/mach-octeon/include/mach/ |
| A D | octeon_ddr.h | 583 enum ddr_type { enum
728 int ddr_type);
773 int ddr_type);
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| /u-boot/board/myir/mys_6ulx/ |
| A D | spl.c | 66 .ddr_type = DDR_TYPE_DDR3,
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| /u-boot/board/phytec/pcl063/ |
| A D | spl.c | 68 .ddr_type = DDR_TYPE_DDR3,
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| /u-boot/board/seeed/npi_imx6ull/ |
| A D | spl.c | 66 .ddr_type = DDR_TYPE_DDR3,
|