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Searched refs:dev_num (Results 1 – 25 of 59) sorted by relevance

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/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_training_ip_flow.h80 int ddr3_tip_bus_read_modify_write(u32 dev_num,
94 int ddr3_tip_adjust_dqs(u32 dev_num);
95 int ddr3_tip_init_controller(u32 dev_num);
102 int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num);
106 int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num);
107 int ddr3_tip_static_init_controller(u32 dev_num);
108 int ddr3_tip_configure_phy(u32 dev_num);
119 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
120 int ddr3_tip_reset_fifo_ptr(u32 dev_num);
121 int ddr3_tip_read_adll_value(u32 dev_num,
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A Dddr3_training_ip_prv_if.h31 u8 dev_num, enum mv_ddr_freq freq,
34 u8 dev_num, struct ddr3_device_info *info_ptr);
38 u8 dev_num, u32 if_id, enum mv_ddr_freq freq);
54 u32 dev_num, enum hws_algo_type algo_type);
59 u32 dev_num, struct init_cntr_param *init_cntr_prm);
63 u32 dev_num, int enable);
65 u32 dev_num, struct mv_ddr_topology_map *tm);
67 u32 dev_num, enum mv_ddr_freq frequency,
109 int ddr3_tip_init_config_func(u32 dev_num,
111 int ddr3_tip_register_xsb_info(u32 dev_num,
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A Dddr3_training.c1429 config_func_info[dev_num].tip_set_freq_divider_func(dev_num, if_id, in ddr3_tip_freq_set()
2160 (u8)dev_num, if_id, freq); in ddr3_tip_ddr3_training_main_flow()
2174 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2187 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2219 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2234 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2281 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2302 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2344 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2594 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
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A Dmv_ddr4_training.c20 static int a39x_z1_config(u32 dev_num);
37 int mv_ddr4_sdram_config(u32 dev_num) in mv_ddr4_sdram_config() argument
99 a39x_z1_config(dev_num); in mv_ddr4_sdram_config()
201 int mv_ddr4_phy_config(u32 dev_num) in mv_ddr4_phy_config() argument
468 static int a39x_z1_config(u32 dev_num) in a39x_z1_config() argument
493 int mv_ddr4_training_main_flow(u32 dev_num) in mv_ddr4_training_main_flow() argument
503 ddr3_tip_reg_dump(dev_num); in mv_ddr4_training_main_flow()
516 ddr3_tip_reg_dump(dev_num); in mv_ddr4_training_main_flow()
529 ddr3_tip_reg_dump(dev_num); in mv_ddr4_training_main_flow()
542 ddr3_tip_reg_dump(dev_num); in mv_ddr4_training_main_flow()
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A Dmv_ddr4_mpr_pda_if.c37 int mv_ddr4_mode_regs_init(u8 dev_num) in mv_ddr4_mode_regs_init() argument
88 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR0_REG, in mv_ddr4_mode_regs_init()
103 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR1_REG, in mv_ddr4_mode_regs_init()
222 static int mv_ddr4_mpr_mode_disable(u8 dev_num) in mv_ddr4_mpr_mode_disable() argument
251 static int mv_ddr4_dq_decode(u8 dev_num, u32 *data) in mv_ddr4_dq_decode() argument
286 int mv_ddr4_mpr_read(u8 dev_num, u32 mpr_num, u32 page_num, in mv_ddr4_mpr_read() argument
310 mv_ddr4_mpr_mode_disable(dev_num); in mv_ddr4_mpr_read()
315 mv_ddr4_dq_decode(dev_num, data); in mv_ddr4_mpr_read()
380 int mv_ddr4_dq_pins_mapping(u8 dev_num) in mv_ddr4_dq_pins_mapping() argument
400 mv_ddr4_mpr_read(dev_num, mpr_type, 0, MV_DDR4_MPR_READ_PARALLEL, in mv_ddr4_dq_pins_mapping()
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A Dddr3_training_leveling.c219 (dev_num, in ddr3_tip_dynamic_read_leveling()
277 ddr3_tip_bus_write(dev_num, in ddr3_tip_dynamic_read_leveling()
299 (dev_num, if_id)); in ddr3_tip_dynamic_read_leveling()
585 (dev_num, in ddr3_tip_dynamic_per_bit_read_leveling()
602 (dev_num, in ddr3_tip_dynamic_per_bit_read_leveling()
658 (dev_num, in ddr3_tip_dynamic_per_bit_read_leveling()
751 (dev_num, if_id)); in ddr3_tip_dynamic_per_bit_read_leveling()
974 (dev_num, in ddr3_tip_dynamic_write_leveling()
1078 dev_num, in ddr3_tip_dynamic_write_leveling()
1093 (dev_num, in ddr3_tip_dynamic_write_leveling()
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A Dmv_ddr4_training_leveling.c11 static int mv_ddr4_dynamic_pb_wl_supp(u32 dev_num, enum mv_wl_supp_mode ecc_mode);
18 static u8 mv_ddr4_xsb_comp_test(u32 dev_num, u32 subphy_num, u32 if_id, in mv_ddr4_xsb_comp_test() argument
84 ddr3_tip_load_pattern_to_mem(dev_num, PATTERN_TEST); in mv_ddr4_xsb_comp_test()
102 ddr3_tip_load_pattern_to_mem(dev_num, PATTERN_TEST); in mv_ddr4_xsb_comp_test()
113 ddr3_tip_load_pattern_to_mem(dev_num, PATTERN_TEST); in mv_ddr4_xsb_comp_test()
120 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE, in mv_ddr4_xsb_comp_test()
126 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE, in mv_ddr4_xsb_comp_test()
247 int mv_ddr4_dynamic_wl_supp(u32 dev_num) in mv_ddr4_dynamic_wl_supp() argument
363 ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id, in mv_ddr4_dynamic_pb_wl_supp()
370 ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id, in mv_ddr4_dynamic_pb_wl_supp()
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A Dddr3_debug.c133 int ddr3_tip_reg_dump(u32 dev_num) in ddr3_tip_reg_dump() argument
164 (dev_num, if_id, in ddr3_tip_reg_dump()
175 (dev_num, if_id, in ddr3_tip_reg_dump()
217 return config_func_info[dev_num]. in ddr3_tip_get_device_info()
324 int print_device_info(u8 dev_num) in print_device_info() argument
398 ddr3_tip_reg_dump(dev_num); in ddr3_tip_print_log()
964 (dev_num, if_id, in ddr3_tip_print_adll()
1143 (dev_num, in ddr3_tip_run_sweep_test()
1201 print_adll(dev_num, ctrl_adll); in ddr3_tip_run_sweep_test()
1395 print_adll(dev_num, ctrl_adll); in ddr3_tip_run_leveling_sweep_test()
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A Dmv_ddr4_mpr_pda_if.h38 int mv_ddr4_mode_regs_init(u8 dev_num);
39 int mv_ddr4_mpr_read(u8 dev_num, u32 mpr_num, u32 page_num,
43 int mv_ddr4_mpr_write(u8 dev_num, u32 mpr_location, u32 mpr_num,
45 int mv_ddr4_dq_pins_mapping(u8 dev_num);
46 int mv_ddr4_vref_training_mode_ctrl(u8 dev_num, u8 if_id,
49 int mv_ddr4_vref_tap_set(u8 dev_num, u8 if_id,
53 int mv_ddr4_vref_set(u8 dev_num, u8 if_id, enum hws_access_type access_type,
55 int mv_ddr4_pda_pattern_odpg_load(u32 dev_num, enum hws_access_type access_type,
57 int mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable);
A Dddr3_training_ip_bist.h35 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
37 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
44 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
46 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
48 int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num,
50 int ddr3_tip_print_regs(u32 dev_num);
51 int ddr3_tip_reg_dump(u32 dev_num);
52 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
A Dddr3_init.h146 int ddr3_tip_enable_init_sequence(u32 dev_num);
155 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
159 int mv_ddr4_mode_regs_init(u8 dev_num);
160 int mv_ddr4_sdram_config(u32 dev_num);
161 int mv_ddr4_phy_config(u32 dev_num);
162 int mv_ddr4_calibration_adjust(u32 dev_num, u8 vref_en, u8 pod_only);
163 int mv_ddr4_training_main_flow(u32 dev_num);
167 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
172 int ddr3_tip_restore_dunit_regs(u32 dev_num);
180 int ddr3_tip_tune_training_params(u32 dev_num,
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A Dddr3_training_ip_engine.c651 (dev_num, access_type, in ddr3_tip_ip_training()
751 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
757 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
935 (dev_num, in ddr3_tip_read_training_result()
1327 (dev_num, if_id, in ddr3_tip_ip_training_wrapper()
1423 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_ip_training_wrapper()
1460 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_ip_training_wrapper()
1618 (dev_num, if_id, in ddr3_tip_load_phy_values()
1625 (dev_num, if_id, in ddr3_tip_load_phy_values()
1632 (dev_num, if_id, in ddr3_tip_load_phy_values()
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A Dddr3_training_ip_centralization.h9 int ddr3_tip_centralization_tx(u32 dev_num);
10 int ddr3_tip_centralization_rx(u32 dev_num);
11 int ddr3_tip_print_centralization_result(u32 dev_num);
12 int ddr3_tip_special_rx(u32 dev_num);
A Dmv_ddr4_training.h12 int mv_ddr4_sdram_config(u32 dev_num);
15 int mv_ddr4_phy_config(u32 dev_num);
21 int mv_ddr4_calibration_adjust(u32 dev_num, u8 vref_en, u8 pod_only);
27 int mv_ddr4_calibration_validate(u32 dev_num);
A Dddr3_training_hw_algo.c77 (dev_num, if_id, in ddr3_tip_write_additional_odt_setting()
201 (dev_num, if_id, in ddr3_tip_vref()
375 (dev_num, if_id, in ddr3_tip_vref()
381 (dev_num, in ddr3_tip_vref()
490 (dev_num, if_id, in ddr3_tip_vref()
496 (dev_num, in ddr3_tip_vref()
533 (dev_num, if_id, in ddr3_tip_vref()
539 (dev_num, in ddr3_tip_vref()
563 (dev_num, if_id, in ddr3_tip_vref()
569 (dev_num, in ddr3_tip_vref()
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A Dddr3_training_centralization.c36 int ddr3_tip_centralization_rx(u32 dev_num) in ddr3_tip_centralization_rx() argument
149 (dev_num, if_id, in ddr3_tip_centralization()
470 ddr3_tip_bus_read(dev_num, if_id, in ddr3_tip_centralization()
492 ddr3_tip_bus_write(dev_num, in ddr3_tip_centralization()
526 int ddr3_tip_special_rx(u32 dev_num) in ddr3_tip_special_rx() argument
587 (dev_num, if_id, in ddr3_tip_special_rx()
656 (dev_num, if_id, in ddr3_tip_special_rx()
664 (dev_num, in ddr3_tip_special_rx()
680 (dev_num, if_id, in ddr3_tip_special_rx()
693 (dev_num, if_id, in ddr3_tip_special_rx()
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A Dddr3_training_pbs.c103 (dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_pbs()
250 (dev_num, in ddr3_tip_pbs()
260 (dev_num, in ddr3_tip_pbs()
280 (dev_num, in ddr3_tip_pbs()
290 (dev_num, in ddr3_tip_pbs()
492 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_pbs()
499 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_pbs()
514 ddr3_tip_ip_training(dev_num, in ddr3_tip_pbs()
530 (dev_num, in ddr3_tip_pbs()
633 (dev_num, in ddr3_tip_pbs()
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A Dmv_ddr_plat.c270 static u32 ddr3_ctrl_get_junc_temp(u8 dev_num) in ddr3_ctrl_get_junc_temp() argument
750 ddr3_tip_init_config_func(dev_num, &config_func); in mv_ddr_sw_db_init()
755 ddr3_tip_dev_attr_init(dev_num); in mv_ddr_sw_db_init()
1490 int ddr3_tip_configure_phy(u32 dev_num) in ddr3_tip_configure_phy() argument
1497 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1502 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1507 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1540 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_configure_phy()
1547 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_configure_phy()
1561 mv_ddr4_phy_config(dev_num); in ddr3_tip_configure_phy()
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A Dddr3_training_hw_algo.h9 int ddr3_tip_vref(u32 dev_num);
10 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
11 int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
A Dddr3_training_ip_pbs.h36 int ddr3_tip_pbs_rx(u32 dev_num);
37 int ddr3_tip_print_all_pbs_result(u32 dev_num);
38 int ddr3_tip_pbs_tx(u32 dev_num);
A Dddr3_training_ip_engine.h33 int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
40 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
41 int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
42 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
52 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
63 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
A Dddr3_training_ip.h153 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
154 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
155 int hws_ddr3_tip_init_controller(u32 dev_num,
157 int hws_ddr3_tip_load_topology_map(u32 dev_num,
159 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
A Dddr3_training_leveling.h11 int ddr3_tip_print_wl_supp_result(u32 dev_num);
12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
/u-boot/lib/fwu_updates/
A Dfwu_gpt.c36 static int fwu_alt_num_for_dfu_dev(struct dfu_entity *dfu, int dev_num, in fwu_alt_num_for_dfu_dev() argument
45 dfu->data.mmc.dev_num == dev_num && in fwu_alt_num_for_dfu_dev()
64 int i, part, dev_num; in fwu_gpt_get_alt_num() local
67 dev_num = desc->devnum; in fwu_gpt_get_alt_num()
87 ret = fwu_alt_num_for_dfu_dev(dfu, dev_num, part, dfu_dev, in fwu_gpt_get_alt_num()
/u-boot/include/
A Dnetdev.h33 int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num);
35 int cs8900_initialize(u8 dev_num, int base_addr);
42 int ep93xx_eth_initialize(u8 dev_num, int base_addr);
44 int ethoc_initialize(u8 dev_num, int base_addr);
51 int ks8851_mll_initialize(u8 dev_num, int base_addr);
52 int lan91c96_initialize(u8 dev_num, int base_addr);
71 int smc91111_initialize(u8 dev_num, phys_addr_t base_addr);
72 int smc911x_initialize(u8 dev_num, phys_addr_t base_addr);

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