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Searched refs:dev_read_u32_default (Results 1 – 25 of 176) sorted by relevance

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/u-boot/drivers/ram/
A Dmpc83xx_sdram.c408 ddr_type = dev_read_u32_default(dev, "ddr_type", 0); in mpc83xx_sdram_probe()
415 mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0); in mpc83xx_sdram_probe()
422 m_odr = dev_read_u32_default(dev, "m_odr", 0); in mpc83xx_sdram_probe()
663 dev_read_u32_default(dev, "activate_to_activate", 0); in mpc83xx_sdram_probe()
797 ecc = dev_read_u32_default(dev, "ecc", 0); in mpc83xx_sdram_probe()
863 timing_2t = dev_read_u32_default(dev, "timing_2t", 0); in mpc83xx_sdram_probe()
946 dll_reset = dev_read_u32_default(dev, "dll_reset", 0); in mpc83xx_sdram_probe()
995 sdmode = dev_read_u32_default(dev, "sdmode", 0); in mpc83xx_sdram_probe()
1002 esdmode = dev_read_u32_default(dev, "esdmode", 0); in mpc83xx_sdram_probe()
1013 esdmode2 = dev_read_u32_default(dev, "esdmode2", 0); in mpc83xx_sdram_probe()
[all …]
/u-boot/drivers/cpu/
A Dmicroblaze_cpu.c57 ci->icache_size = dev_read_u32_default(dev, "i-cache-size", 0); in microblaze_set_cpuinfo_static()
58 ci->icache_line_length = dev_read_u32_default(dev, in microblaze_set_cpuinfo_static()
61 ci->dcache_size = dev_read_u32_default(dev, "d-cache-size", 0); in microblaze_set_cpuinfo_static()
62 ci->dcache_line_length = dev_read_u32_default(dev, in microblaze_set_cpuinfo_static()
65 ci->cpu_freq = dev_read_u32_default(dev, "clock-frequency", 0); in microblaze_set_cpuinfo_static()
66 ci->addr_size = dev_read_u32_default(dev, "xlnx,addr-size", 32); in microblaze_set_cpuinfo_static()
67 ci->use_mmu = dev_read_u32_default(dev, "xlnx,use-mmu", 0); in microblaze_set_cpuinfo_static()
/u-boot/drivers/mmc/
A Dnexell_dw_mmc.c154 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); in nexell_dwmmc_of_to_plat()
159 val = dev_read_u32_default(dev, "index", -1); in nexell_dwmmc_of_to_plat()
166 priv->fifo_size = dev_read_u32_default(dev, "fifo-size", 0x20); in nexell_dwmmc_of_to_plat()
168 priv->frequency = dev_read_u32_default(dev, "frequency", 50000000); in nexell_dwmmc_of_to_plat()
169 priv->max_freq = dev_read_u32_default(dev, "max-frequency", 50000000); in nexell_dwmmc_of_to_plat()
171 priv->d_delay = dev_read_u32_default(dev, "drive_dly", 0); in nexell_dwmmc_of_to_plat()
172 priv->d_shift = dev_read_u32_default(dev, "drive_shift", 3); in nexell_dwmmc_of_to_plat()
173 priv->s_delay = dev_read_u32_default(dev, "sample_dly", 0); in nexell_dwmmc_of_to_plat()
174 priv->s_shift = dev_read_u32_default(dev, "sample_shift", 2); in nexell_dwmmc_of_to_plat()
175 priv->mmcboost = dev_read_u32_default(dev, "mmcboost", 0); in nexell_dwmmc_of_to_plat()
A Dnpcm_sdhci.c30 host->max_clk = dev_read_u32_default(dev, "clock-frequency", 0); in npcm_sdhci_probe()
41 vqmmc_uv = dev_read_u32_default(dev, "vqmmc-microvolt", 0); in npcm_sdhci_probe()
47 host->index = dev_read_u32_default(dev, "index", 0); in npcm_sdhci_probe()
A Dca_dw_mmc.c102 host->buswidth = dev_read_u32_default(dev, "bus-width", 1); in ca_dwmmc_of_to_plat()
103 host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000); in ca_dwmmc_of_to_plat()
104 priv->ds = dev_read_u32_default(dev, "io_ds", 0x33); in ca_dwmmc_of_to_plat()
A Drockchip_dw_mmc.c71 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); in rockchip_dwmmc_of_to_plat()
81 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); in rockchip_dwmmc_of_to_plat()
97 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); in rockchip_dwmmc_of_to_plat()
A Df_sdh30.c101 host->bus_width = dev_read_u32_default(dev, "bus-width", 4); in f_sdh30_of_to_plat()
102 host->index = dev_read_u32_default(dev, "index", 0); in f_sdh30_of_to_plat()
/u-boot/drivers/video/tegra20/
A Dtegra-pwm-backlight.c121 dev_read_u32_default(dev, "nvidia,pwm-source", in tegra_pwm_backlight_probe()
124 dev_read_u32_default(dev, "nvidia,period", in tegra_pwm_backlight_probe()
127 dev_read_u32_default(dev, "nvidia,clock-div", in tegra_pwm_backlight_probe()
130 dev_read_u32_default(dev, "nvidia,clock-select", in tegra_pwm_backlight_probe()
133 dev_read_u32_default(dev, "nvidia,default-brightness", in tegra_pwm_backlight_probe()
/u-boot/drivers/gpio/
A Dxilinx_gpio.c273 plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0); in xilinx_gpio_of_to_plat()
274 plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0); in xilinx_gpio_of_to_plat()
275 plat->bank_output[0] = dev_read_u32_default(dev, "xlnx,all-outputs", 0); in xilinx_gpio_of_to_plat()
276 plat->dout_default[0] = dev_read_u32_default(dev, "xlnx,dout-default", in xilinx_gpio_of_to_plat()
279 is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0); in xilinx_gpio_of_to_plat()
281 plat->bank_max[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
283 plat->bank_input[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
285 plat->bank_output[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
287 plat->dout_default[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
A Dhsdk-creg-gpio.c87 gpio_count = dev_read_u32_default(dev, "gpio-count", 1); in hsdk_creg_gpio_probe()
88 shift = dev_read_u32_default(dev, "gpio-first-shift", 0); in hsdk_creg_gpio_probe()
89 bit_per_gpio = dev_read_u32_default(dev, "gpio-bit-per-line", 1); in hsdk_creg_gpio_probe()
90 activate = dev_read_u32_default(dev, "gpio-activate-val", 1); in hsdk_creg_gpio_probe()
91 deactivate = dev_read_u32_default(dev, "gpio-deactivate-val", 0); in hsdk_creg_gpio_probe()
/u-boot/drivers/led/
A Dled_cortina.c142 dev_read_u32_default(dev, "Cortina,blink-rate1", 256); in ca_led_of_to_plat()
144 dev_read_u32_default(dev, "Cortina,blink-rate2", 512); in ca_led_of_to_plat()
150 priv->pin = dev_read_u32_default(dev, "pin", LED_MAX_COUNT); in ca_led_of_to_plat()
151 priv->blink_sel = dev_read_u32_default(dev, "blink-sel", 0); in ca_led_of_to_plat()
152 priv->off_event = dev_read_u32_default(dev, "off-event", 0); in ca_led_of_to_plat()
153 priv->blink_event = dev_read_u32_default(dev, "blink-event", 0); in ca_led_of_to_plat()
154 priv->on_event = dev_read_u32_default(dev, "on-event", 0); in ca_led_of_to_plat()
155 priv->port = dev_read_u32_default(dev, "port", 0); in ca_led_of_to_plat()
A Dled_bcm6358.c130 clk_div = dev_read_u32_default(dev, "brcm,clk-div", in bcm6358_led_probe()
159 pin = dev_read_u32_default(dev, "reg", LEDS_MAX); in bcm6358_led_probe()
A Dled_pwm.c121 def_brightness = dev_read_u32_default(dev, "u-boot,default-brightness", 0); in led_pwm_of_to_plat()
122 max_brightness = dev_read_u32_default(dev, "max-brightness", 255); in led_pwm_of_to_plat()
/u-boot/drivers/sysreset/
A Dpoweroff_gpio.c69 priv->active_delay_ms = dev_read_u32_default(dev, "active-delay-ms", 100); in poweroff_gpio_probe()
70 priv->inactive_delay_ms = dev_read_u32_default(dev, "inactive-delay-ms", 100); in poweroff_gpio_probe()
71 priv->timeout_ms = dev_read_u32_default(dev, "timeout-ms", 3000); in poweroff_gpio_probe()
/u-boot/drivers/video/
A Dsandbox_sdl.c121 plat->xres = dev_read_u32_default(dev, "xres", LCD_MAX_WIDTH); in sandbox_sdl_bind()
122 plat->yres = dev_read_u32_default(dev, "yres", LCD_MAX_HEIGHT); in sandbox_sdl_bind()
123 l2bpp = dev_read_u32_default(dev, "log2-depth", VIDEO_BPP16); in sandbox_sdl_bind()
124 plat->rot = dev_read_u32_default(dev, "rotate", 0); in sandbox_sdl_bind()
/u-boot/drivers/power/regulator/
A Dregulator_common.c39 dev_pdata->startup_delay_us = dev_read_u32_default(dev, in regulator_common_of_to_plat()
42 dev_read_u32_default(dev, "off-on-delay-us", 0); in regulator_common_of_to_plat()
45 dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0); in regulator_common_of_to_plat()
A Dregulator-uclass.c451 uc_pdata->min_uV = dev_read_u32_default(dev, "regulator-min-microvolt", in regulator_pre_probe()
453 uc_pdata->max_uV = dev_read_u32_default(dev, "regulator-max-microvolt", in regulator_pre_probe()
455 uc_pdata->init_uV = dev_read_u32_default(dev, "regulator-init-microvolt", in regulator_pre_probe()
457 uc_pdata->min_uA = dev_read_u32_default(dev, "regulator-min-microamp", in regulator_pre_probe()
459 uc_pdata->max_uA = dev_read_u32_default(dev, "regulator-max-microamp", in regulator_pre_probe()
463 uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", in regulator_pre_probe()
/u-boot/drivers/reset/
A Dreset-syscon.c62 priv->offset = dev_read_u32_default(dev, "offset", 0); in syscon_reset_probe()
63 priv->mask = dev_read_u32_default(dev, "mask", 0); in syscon_reset_probe()
64 priv->assert_high = dev_read_u32_default(dev, "assert-high", true); in syscon_reset_probe()
/u-boot/drivers/clk/
A Dclk_fixed_factor.c54 ff->div = dev_read_u32_default(dev, "clock-div", 1); in clk_fixed_factor_of_to_plat()
55 ff->mult = dev_read_u32_default(dev, "clock-mult", 1); in clk_fixed_factor_of_to_plat()
/u-boot/drivers/net/octeon/
A Docteon_mdio.c155 drv_ctl.s.pctl = dev_read_u32_default(dev, "cavium,pctl-drive-strength", in octeon_mdio_probe()
157 drv_ctl.s.nctl = dev_read_u32_default(dev, "cavium,nctl-drive-strength", in octeon_mdio_probe()
164 p->speed = dev_read_u32_default(dev, "cavium,max-speed", in octeon_mdio_probe()
171 sample_dly = dev_read_u32_default(dev, "cavium,sample-delay", 0); in octeon_mdio_probe()
/u-boot/drivers/net/
A Deth-phy-uclass.c144 uc_priv->reset_assert_delay = dev_read_u32_default(dev, "reset-assert-us", 0); in eth_phy_of_to_plat()
145 uc_priv->reset_deassert_delay = dev_read_u32_default(dev, "reset-deassert-us", 0); in eth_phy_of_to_plat()
/u-boot/drivers/serial/
A Dserial_omap.c116 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); in omap_serial_of_to_plat()
130 plat->clock = dev_read_u32_default(dev, "clock-frequency", in omap_serial_of_to_plat()
/u-boot/drivers/remoteproc/
A Dti_k3_arm64_rproc.c158 tsp->proc_id = dev_read_u32_default(dev, "ti,sci-proc-id", INVALID_ID); in ti_sci_proc_of_to_priv()
163 tsp->host_id = dev_read_u32_default(dev, "ti,sci-host-id", INVALID_ID); in ti_sci_proc_of_to_priv()
/u-boot/drivers/input/
A Dcros_ec_keyb.c188 config->key_rows = dev_read_u32_default(dev, "keypad,num-rows", 0); in cros_ec_keyb_decode_fdt()
189 config->key_cols = dev_read_u32_default(dev, "keypad,num-columns", 0); in cros_ec_keyb_decode_fdt()
/u-boot/drivers/spi/
A Dspi-uclass.c197 spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); in spi_post_probe()
545 plat->cs = dev_read_u32_default(dev, "reg", -1); in spi_slave_of_to_plat()
546 plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", in spi_slave_of_to_plat()
560 value = dev_read_u32_default(dev, "spi-tx-bus-width", 1); in spi_slave_of_to_plat()
578 value = dev_read_u32_default(dev, "spi-rx-bus-width", 1); in spi_slave_of_to_plat()

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