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Searched refs:div (Results 1 – 25 of 263) sorted by relevance

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/u-boot/arch/mips/mach-ath79/qca953x/
A Dclk.c48 pll = xtal / div; in get_clocks()
53 pll *= div; in get_clocks()
56 if (!div) in get_clocks()
57 div = 1; in get_clocks()
58 pll >>= div; in get_clocks()
63 gd->cpu_clk = pll / div; in get_clocks()
70 pll = xtal / div; in get_clocks()
75 pll *= div; in get_clocks()
78 if (!div) in get_clocks()
79 div = 1; in get_clocks()
[all …]
/u-boot/drivers/clk/
A Dclk-divider.c65 unsigned int div; in divider_recalc_rate() local
68 if (!div) { in divider_recalc_rate()
102 if (clkt->div == div) in clk_divider_is_valid_table_div()
123 if (clkt->div == div) in clk_divider_get_table_val()
132 return div; in _get_val()
136 return (div == clk_div_mask(width) + 1) ? 0 : div; in _get_val()
139 return div - 1; in _get_val()
203 div = kzalloc(sizeof(*div), GFP_KERNEL); in _register_divider()
204 if (!div) in _register_divider()
208 div->reg = reg; in _register_divider()
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A Dclk-fixed-factor.c33 do_div(rate, fix->div); in clk_factor_recalc_rate()
43 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor() argument
55 fix->div = div; in clk_hw_register_fixed_factor()
71 unsigned int mult, unsigned int div) in clk_register_fixed_factor() argument
76 div); in clk_register_fixed_factor()
/u-boot/arch/mips/mach-ath79/ar933x/
A Dclk.c36 u32 val, xtal, pll, div; in get_clocks() local
44 div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) in get_clocks()
46 pll = xtal / div; in get_clocks()
49 div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) in get_clocks()
51 pll *= div; in get_clocks()
54 if (!div) in get_clocks()
55 div = 1; in get_clocks()
56 pll >>= div; in get_clocks()
63 gd->cpu_clk = pll / div; in get_clocks()
68 gd->mem_clk = pll / div; in get_clocks()
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/u-boot/arch/arm/mach-s5pc1xx/
A Dclock.c133 unsigned long div; in s5pc110_get_arm_clk() local
137 div = readl(&clk->div0); in s5pc110_get_arm_clk()
140 apll_ratio = div & 0x7; in s5pc110_get_arm_clk()
153 unsigned long div; in s5pc100_get_arm_clk() local
157 div = readl(&clk->div0); in s5pc100_get_arm_clk()
162 apll_ratio = div & 0x1; in s5pc100_get_arm_clk()
176 uint div, d0_bus_ratio; in get_hclk() local
178 div = readl(&clk->div0); in get_hclk()
195 div = readl(&clk->div0); in get_pclkd1()
214 unsigned int div; in get_hclk_sys() local
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/u-boot/drivers/clk/rockchip/
A Dclk_rv1108.c35 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
78 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
79 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
82 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
153 uint8_t div; in rv1108_mac_set_clk() local
178 u32 div; in rv1108_sfc_set_clk() local
197 u32 div, val; in rv1108_saradc_get_clk() local
222 u32 div, val; in rv1108_aclk_vio1_get_clk() local
248 u32 div, val; in rv1108_aclk_vio0_get_clk() local
283 u32 div, val; in rv1108_dclk_vop_get_clk() local
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A Dclk_rk3328.c35 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
246 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
247 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
251 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
338 u32 div, con; in rk3328_i2c_get_clk() local
427 u8 div; in rk3328_gmac2io_set_clk() local
435 if (div <= 0x1f) in rk3328_gmac2io_set_clk()
514 u32 div, con; in rk3328_pwm_get_clk() local
536 u32 div, val; in rk3328_saradc_get_clk() local
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A Dclk_rk3128.c31 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
49 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
50 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
53 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
65 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
131 div->refdiv = refdiv; in pll_para_config()
132 div->fbdiv = fbdiv; in pll_para_config()
286 uint div, mux; in rockchip_mmc_get_clk() local
352 u32 div, con; in rk3128_peri_get_pclk() local
397 u32 div, val; in rk3128_saradc_get_clk() local
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A Dclk_rk3588.c24 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
888 u32 div; in rk3588_aux16m_set_clk() local
974 div = 1; in rk3588_aclk_vop_set_clk()
977 div = 2; in rk3588_aclk_vop_set_clk()
980 div = 1; in rk3588_aclk_vop_set_clk()
1182 u32 con, div; in rk3588_gmac_get_clk() local
1210 int div; in rk3588_gmac_set_clk() local
1326 div = 2; in rk3588_uart_set_rate()
1330 div = 2; in rk3588_uart_set_rate()
1425 div = 1; in rk3588_pciephy_set_rate()
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A Dclk_rk3368.c46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
98 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
102 pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
164 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
228 u32 adj_div = div; in rk3368_mmc_find_best_rate_and_parent()
245 *best_div = div - 1; in rk3368_mmc_find_best_rate_and_parent()
280 mux | div); in rk3368_mmc_set_clk()
331 u8 div; in rk3368_gmac_set_clk() local
344 if (div <= 0x1f) in rk3368_gmac_set_clk()
386 u32 div, val; in rk3368_spi_get_clk() local
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A Dclk_rk3308.c33 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
132 u32 div, con, con_id; in rk3308_i2c_get_clk() local
198 u8 div; in rk3308_mac_set_clk() local
215 assert(div < 32); in rk3308_mac_set_clk()
242 u32 div, con, con_id; in rk3308_mmc_get_clk() local
314 u32 div, con; in rk3308_saradc_get_clk() local
342 u32 div, con; in rk3308_tsadc_get_clk() local
370 u32 div, con, con_id; in rk3308_spi_get_clk() local
429 u32 div, con; in rk3308_pwm_get_clk() local
514 if (div > 255) in rk3308_vop_set_clk()
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A Dclk_rk3288.c157 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
161 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
164 (div->no == 1 || !(div->no % 2))); in rkclk_set_pll()
170 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); in rkclk_set_pll()
269 div->no = no; in pll_para_config()
292 div->nr = nr; in pll_para_config()
293 div->nf = nf; in pll_para_config()
319 u8 div; in rockchip_mac_set_clk() local
727 u32 div, val; in rockchip_saradc_get_clk() local
847 u32 div; in rk3288_clk_set_rate() local
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/u-boot/drivers/clk/renesas/
A Drcar-cpg-lib.c56 for (clkt = table; clkt->div; clkt++) in rcar_clk_get_table_div()
58 return clkt->div; in rcar_clk_get_table_div()
63 unsigned int div) in rcar_clk_get_table_val() argument
67 for (clkt = table; clkt->div; clkt++) in rcar_clk_get_table_val()
68 if (clkt->div == div) in rcar_clk_get_table_val()
77 u32 value, div; in rcar_clk_get_rate64_div_table() local
81 div = rcar_clk_get_table_div(table, value); in rcar_clk_get_rate64_div_table()
82 if (!div) in rcar_clk_get_rate64_div_table()
85 rate = parent_rate / div; in rcar_clk_get_rate64_div_table()
96 u32 value = 0, div = 0; in rcar_clk_set_rate64_div_table() local
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/u-boot/drivers/clk/ti/
A Dclk-divider.c60 return div; in _get_val()
79 if (clkt->div == div) in _div_round_up()
81 else if (clkt->div < div) in _div_round_up()
84 if ((clkt->div - div) < (up - div)) in _div_round_up()
175 int div; in clk_ti_divider_round_rate() local
178 if (div < 0) in clk_ti_divider_round_rate()
179 return div; in clk_ti_divider_round_rate()
188 int div; in clk_ti_divider_set_rate() local
192 if (div < 0) in clk_ti_divider_set_rate()
193 return div; in clk_ti_divider_set_rate()
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A Dclk-k3.c125 name = ti_clk_data->clk.div.name; in ti_clk_probe()
128 ti_clk_data->clk.div.flags, in ti_clk_probe()
130 ti_clk_data->clk.div.shift, in ti_clk_probe()
131 ti_clk_data->clk.div.width, in ti_clk_probe()
240 int div = 1; in ti_clk_set_rate() local
275 diff = abs(new_rate - rate / div); in ti_clk_set_rate()
286 if (diff > rate / div / 2) { in ti_clk_set_rate()
293 __func__, (u32)rate / div); in ti_clk_set_rate()
310 pll_div = rate / div / osc_freq; in ti_clk_set_rate()
318 return clk_set_rate(clk, rate / div) * div; in ti_clk_set_rate()
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/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dclock.c42 uint32_t clkctrl, clkseq, div; in mxs_get_pclk() local
59 return XTAL_FREQ_MHZ / div; in mxs_get_pclk()
74 uint32_t div; in mxs_get_hclk() local
84 return mxs_get_pclk() / div; in mxs_get_hclk()
102 return XTAL_FREQ_MHZ / div; in mxs_get_emiclk()
132 return XTAL_FREQ_MHZ / div; in mxs_get_gpmiclk()
149 uint32_t div; in mxs_set_ioclk() local
160 if (div < 18) in mxs_set_ioclk()
161 div = 18; in mxs_set_ioclk()
163 if (div > 35) in mxs_set_ioclk()
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/u-boot/drivers/clk/nuvoton/
A Dclk_npcm.c119 u32 val, div; in npcm_clk_get_div() local
128 div = div + 1; in npcm_clk_get_div()
130 div = 1 << div; in npcm_clk_get_div()
133 div = div << 1; in npcm_clk_get_div()
135 return div; in npcm_clk_get_div()
149 div = div >> 1; in npcm_clk_set_div()
152 clkdiv = div - 1; in npcm_clk_set_div()
154 clkdiv = ilog2(div); in npcm_clk_set_div()
167 u32 div; in npcm_clk_get_fout() local
174 if (!div) in npcm_clk_get_fout()
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/u-boot/lib/
A Dtiny-printf.c38 unsigned long div) in div_out() argument
42 while (*num >= div) { in div_out()
43 *num -= div; in div_out()
166 unsigned long div; in pointer() local
195 for (; div; div /= 0x10) in pointer()
206 unsigned long div; in _vprintf() local
247 div = 1000000000; in _vprintf()
251 div *= div * 10; in _vprintf()
268 for (; div; div /= 10) in _vprintf()
292 div = 0x10000000; in _vprintf()
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/u-boot/drivers/clk/mvebu/
A Darmada-37xx-tbg.c58 unsigned int div[NUM_TBG]; member
73 unsigned int div; in tbg_get_div() local
77 div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK; in tbg_get_div()
78 if (div == 0) in tbg_get_div()
79 div = 1; in tbg_get_div()
82 div *= 1 << ((val >> ptbg->vcodiv_offset) & TBG_DIV_MASK); in tbg_get_div()
84 return div; in tbg_get_div()
128 unsigned int mult, div; in armada_37xx_tbg_clk_probe() local
131 div = tbg_get_div(reg, &tbg[i]); in armada_37xx_tbg_clk_probe()
133 priv->rates[i] = (xtal * mult) / div; in armada_37xx_tbg_clk_probe()
/u-boot/arch/arm/cpu/armv7/s5p-common/
A Dpwm.c51 unsigned int div; in pwm_calc_tin() local
70 div = ((val >> 0) & 0xff) + 1; in pwm_calc_tin()
72 div = ((val >> 8) & 0xff) + 1; in pwm_calc_tin()
79 freq = tin_parent_rate / div / pre_div; in pwm_calc_tin()
83 for (div = 2; div <= 16; div *= 2) { in pwm_calc_tin()
84 if ((tin_parent_rate / (div << 16)) < freq) in pwm_calc_tin()
85 return tin_parent_rate / div; in pwm_calc_tin()
159 int s5p_pwm_init(int pwm_id, int div, int invert) in s5p_pwm_init() argument
189 val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id); in s5p_pwm_init()
206 ((prescaler + 1) * (1 << div)); in s5p_pwm_init()
/u-boot/arch/arm/mach-exynos/
A Dclock.c118 unsigned int div; in exynos_get_pll_clk() local
160 div = PLL_DIV_1024; in exynos_get_pll_clk()
162 div = PLL_DIV_65535; in exynos_get_pll_clk()
454 div = (div >> bit_info->div_bit) & bit_info->div_mask; in exynos5_get_periph_rate()
548 div = (div >> bit_info->div_bit) & bit_info->div_mask; in exynos542x_get_periph_rate()
575 unsigned long div; in exynos4_get_arm_clk() local
597 unsigned long div; in exynos4x12_get_arm_clk() local
619 unsigned long div; in exynos5_get_arm_clk() local
1361 unsigned int div; in exynos5_set_i2s_clk_prescaler() local
1705 if (div > 0) in set_mmc_clk()
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/u-boot/drivers/adc/
A Dstm32-adc-core.c38 int div; member
67 int div; in stm32h7_adc_clk_sel() local
94 div = stm32h7_adc_ckmodes_spec[i].div; in stm32h7_adc_clk_sel()
99 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) in stm32h7_adc_clk_sel()
114 div = stm32h7_adc_ckmodes_spec[i].div; in stm32h7_adc_clk_sel()
119 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) in stm32h7_adc_clk_sel()
128 common->rate = rate / div; in stm32h7_adc_clk_sel()
137 ckmode ? "bus" : "adc", div, common->rate / 1000); in stm32h7_adc_clk_sel()
/u-boot/arch/arm/cpu/armv7/bcm235xx/
A Dclk-core.c114 if (divider_exists(&cd->div)) { in peri_clk_enable()
116 bitfield_replace(reg, cd->div.shift, cd->div.width, in peri_clk_enable()
117 c->div - 1); in peri_clk_enable()
184 div = ref->clk.rate / rate; in peri_clk_set_rate()
185 if (div == 0) in peri_clk_set_rate()
186 div = 1; in peri_clk_set_rate()
196 c->div = div; in peri_clk_set_rate()
211 int div = 1; in peri_clk_get_rate() local
230 div = bitfield_extract(reg, cd->div.shift, cd->div.width); in peri_clk_get_rate()
231 div += 1; in peri_clk_get_rate()
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/u-boot/arch/arm/cpu/armv7/bcm281xx/
A Dclk-core.c114 if (divider_exists(&cd->div)) { in peri_clk_enable()
116 bitfield_replace(reg, cd->div.shift, cd->div.width, in peri_clk_enable()
117 c->div - 1); in peri_clk_enable()
184 div = ref->clk.rate / rate; in peri_clk_set_rate()
185 if (div == 0) in peri_clk_set_rate()
186 div = 1; in peri_clk_set_rate()
196 c->div = div; in peri_clk_set_rate()
211 int div = 1; in peri_clk_get_rate() local
230 div = bitfield_extract(reg, cd->div.shift, cd->div.width); in peri_clk_get_rate()
231 div += 1; in peri_clk_get_rate()
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/u-boot/drivers/clk/imx/
A Dclk-pllv3.c87 u32 val, div; in clk_pllv3_generic_set_rate() local
90 div = 1; in clk_pllv3_generic_set_rate()
92 div = 0; in clk_pllv3_generic_set_rate()
98 val |= (div << pll->div_shift); in clk_pllv3_generic_set_rate()
164 return parent_rate * div / 2; in clk_pllv3_sys_get_rate()
173 u32 val, div; in clk_pllv3_sys_set_rate() local
184 div = rate * 2 / parent_rate; in clk_pllv3_sys_set_rate()
187 val |= div; in clk_pllv3_sys_set_rate()
228 u32 val, div; in clk_pllv3_av_set_rate() local
245 div = rate / parent_rate; in clk_pllv3_av_set_rate()
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