Searched refs:dm_pci_read_config (Results 1 – 4 of 4) sorted by relevance
| /u-boot/cmd/ |
| A D | pci.c | 55 dm_pci_read_config(dev, regs->offset, &val, regs->size); in pci_show_regs()
235 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8); in pci_header_show()
236 dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8); in pci_header_show()
279 dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16); in pci_header_show_brief()
280 dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16); in pci_header_show_brief()
281 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8); in pci_header_show_brief()
282 dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8); in pci_header_show_brief()
374 dm_pci_read_config(dev, addr, &val, size); in pci_cfg_display()
407 dm_pci_read_config(dev, addr, &val, size); in pci_cfg_modify()
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| /u-boot/drivers/pci/ |
| A D | pci-uclass.c | 393 int dm_pci_read_config(const struct udevice *dev, int offset, in dm_pci_read_config() function
448 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8); in dm_pci_read_config8()
461 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16); in dm_pci_read_config16()
474 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32); in dm_pci_read_config32()
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| /u-boot/include/ |
| A D | pci.h | 1089 int dm_pci_read_config(const struct udevice *dev, int offset,
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| /u-boot/doc/board/google/ |
| A D | chromebook_coral.rst | 235 proper PCI access is available and normal dm_pci_read_config() calls can be
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