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Searched refs:dm_pci_write_config32 (Results 1 – 25 of 32) sorted by relevance

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/u-boot/arch/x86/cpu/ivybridge/
A Dnorthbridge.c162 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); in sandybridge_setup_northbridge_bars()
163 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); in sandybridge_setup_northbridge_bars()
164 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); in sandybridge_setup_northbridge_bars()
165 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32); in sandybridge_setup_northbridge_bars()
167 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); in sandybridge_setup_northbridge_bars()
168 dm_pci_write_config32(dev, PCIEXBAR + 4, in sandybridge_setup_northbridge_bars()
170 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); in sandybridge_setup_northbridge_bars()
171 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); in sandybridge_setup_northbridge_bars()
236 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); in bd82x6x_northbridge_early_init()
A Dlpc.c124 dm_pci_write_config32(pch, 0xb8, reg); in pch_gpi_routing()
487 dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, in bd82x6x_lpc_early_init()
489 dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); in bd82x6x_lpc_early_init()
498 dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1); in bd82x6x_lpc_early_init()
499 dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10); in bd82x6x_lpc_early_init()
A Dsata.c27 dm_pci_write_config32(dev, IDE_CONFIG, reg32); in common_sata_init()
37 dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); in common_sata_init()
A Dearly_me.c93 dm_pci_write_config32(dev, ETR3, etr3); in set_global_reset()
/u-boot/arch/x86/cpu/intel_common/
A Dpch.c14 dm_pci_write_config32(dev, SATA_SIRI, idx); in pch_common_sir_read()
22 dm_pci_write_config32(dev, SATA_SIRI, idx); in pch_common_sir_write()
23 dm_pci_write_config32(dev, SATA_SIRD, value); in pch_common_sir_write()
A Dlpc.c34 dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1); in enable_port80_on_lpc()
74 dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg); in lpc_common_early_init()
A Dintel_opregion.c64 dm_pci_write_config32(dev, ASLS, opregion); in intel_gma_opregion_register()
/u-boot/arch/x86/cpu/broadwell/
A Dnorthbridge.c116 dm_pci_write_config32(dev, PCIEXBAR + 4, 0); in broadwell_northbridge_early_init()
118 dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1); in broadwell_northbridge_early_init()
120 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); in broadwell_northbridge_early_init()
121 dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1); in broadwell_northbridge_early_init()
122 dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1); in broadwell_northbridge_early_init()
136 dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); in broadwell_northbridge_early_init()
A Dsata.c69 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init()
80 dm_pci_write_config32(dev, 0x94, reg32); in broadwell_sata_init()
201 dm_pci_write_config32(dev, 0x300, reg32); in broadwell_sata_init()
205 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init()
210 dm_pci_write_config32(dev, 0x9c, reg32); in broadwell_sata_init()
A Dme.c30 dm_pci_write_config32(dev, PCI_ME_H_GS, in intel_me_hsio_version()
54 dm_pci_write_config32(dev, PCI_ME_H_GS, in intel_me_hsio_version()
A Dadsp.c58 dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE); in broadwell_adsp_probe()
86 dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); in broadwell_adsp_probe()
114 dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); in broadwell_adsp_probe()
A Dpch.c46 dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1); in broadwell_pch_early_init()
48 dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1); in broadwell_pch_early_init()
50 dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1); in broadwell_pch_early_init()
/u-boot/drivers/pci/
A Dpci_auto.c70 dm_pci_write_config32(dev, bar, 0xffffffff); in dm_pciauto_setup_device()
94 dm_pci_write_config32(dev, bar + 4, 0xffffffff); in dm_pciauto_setup_device()
128 dm_pci_write_config32(dev, bar, (u32)bar_value); in dm_pciauto_setup_device()
133 dm_pci_write_config32(dev, bar, in dm_pciauto_setup_device()
141 dm_pci_write_config32(dev, bar, 0x00000000); in dm_pciauto_setup_device()
159 dm_pci_write_config32(dev, rom_addr, 0xfffffffe); in dm_pciauto_setup_device()
167 dm_pci_write_config32(dev, rom_addr, bar_value); in dm_pciauto_setup_device()
402 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, in dm_pciauto_prescan_setup_bridge()
405 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0); in dm_pciauto_prescan_setup_bridge()
491 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, in dm_pciauto_postscan_setup_bridge()
[all …]
A Dpci_rom.c96 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, in pci_rom_probe()
111 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address); in pci_rom_probe()
/u-boot/board/intel/cougarcanyon2/
A Dcougarcanyon2.c31 dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B | in board_early_init_f()
33 dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B | in board_early_init_f()
/u-boot/drivers/bios_emulator/
A Datibios.c298 dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF); in PCI_findBIOSAddr()
326 dm_pci_write_config32(pcidev, reg, *base); in PCI_fixupIObase()
375 dm_pci_write_config32(pcidev, BIOSImageBAR, 0); in PCI_mapBIOSImage()
376 dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); in PCI_mapBIOSImage()
398 dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress); in PCI_unmapBIOSImage()
399 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10); in PCI_unmapBIOSImage()
400 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14); in PCI_unmapBIOSImage()
401 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18); in PCI_unmapBIOSImage()
402 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20); in PCI_unmapBIOSImage()
A Dbios.c271 dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
285 dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
/u-boot/arch/x86/cpu/queensbay/
A Dtnc.c52 dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE); in disable_igd()
53 dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE); in disable_igd()
/u-boot/board/imgtec/malta/
A Dmalta.c238 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI, in board_early_init_r()
240 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC, in board_early_init_r()
/u-boot/drivers/i2c/
A Ddesignware_i2c_pci.c50 dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); in designware_i2c_pci_of_to_plat()
53 dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | in designware_i2c_pci_of_to_plat()
/u-boot/arch/x86/cpu/apollolake/
A Dfsp_m.c63 dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0, in fspm_done()
/u-boot/cmd/
A Dpci.c94 dm_pci_write_config32(dev, reg_addr, 0xffffffff); in pci_bar_show()
96 dm_pci_write_config32(dev, reg_addr, base_low); in pci_bar_show()
110 dm_pci_write_config32(dev, reg_addr, 0xffffffff); in pci_bar_show()
112 dm_pci_write_config32(dev, reg_addr, base_high); in pci_bar_show()
/u-boot/drivers/usb/host/
A Dxhci-pci.c49 dm_pci_write_config32(dev, PCI_COMMAND, cmd); in xhci_pci_init()
A Dehci-pci.c54 dm_pci_write_config32(dev, PCI_COMMAND, cmd); in ehci_pci_init()
/u-boot/arch/x86/lib/
A Dbios_interrupts.c199 dm_pci_write_config32(dev, reg, dword); in int1a_handler()

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