| /u-boot/arch/x86/cpu/ivybridge/ |
| A D | lpc.c | 37 dm_pci_write_config8(pch, ACPI_CNTL, 0x80); in pch_enable_apic()
80 dm_pci_write_config8(pch, SERIRQ_CNTL, value); in pch_enable_serial_irqs()
94 dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++); in pch_pirq_init()
95 dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++); in pch_pirq_init()
96 dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++); in pch_pirq_init()
97 dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++); in pch_pirq_init()
99 dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++); in pch_pirq_init()
100 dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++); in pch_pirq_init()
259 dm_pci_write_config8(pch, 0xa9, 0x47); in cpt_pm_init()
303 dm_pci_write_config8(pch, 0xa9, 0x47); in ppt_pm_init()
[all …]
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| A D | northbridge.c | 174 dm_pci_write_config8(dev, PAM0, 0x30); in sandybridge_setup_northbridge_bars()
175 dm_pci_write_config8(dev, PAM1, 0x33); in sandybridge_setup_northbridge_bars()
176 dm_pci_write_config8(dev, PAM2, 0x33); in sandybridge_setup_northbridge_bars()
177 dm_pci_write_config8(dev, PAM3, 0x33); in sandybridge_setup_northbridge_bars()
178 dm_pci_write_config8(dev, PAM4, 0x33); in sandybridge_setup_northbridge_bars()
179 dm_pci_write_config8(dev, PAM5, 0x33); in sandybridge_setup_northbridge_bars()
180 dm_pci_write_config8(dev, PAM6, 0x33); in sandybridge_setup_northbridge_bars()
227 dm_pci_write_config8(dev, 0xf3, reg8); in bd82x6x_northbridge_early_init()
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| A D | sata.c | 110 dm_pci_write_config8(dev, 0x09, 0x80); in bd82x6x_sata_init()
139 dm_pci_write_config8(dev, 0x09, 0x8f); in bd82x6x_sata_init()
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| /u-boot/arch/x86/cpu/broadwell/ |
| A D | northbridge.c | 127 dm_pci_write_config8(dev, PAM0, 0x30); in broadwell_northbridge_early_init()
128 dm_pci_write_config8(dev, PAM1, 0x33); in broadwell_northbridge_early_init()
129 dm_pci_write_config8(dev, PAM2, 0x33); in broadwell_northbridge_early_init()
130 dm_pci_write_config8(dev, PAM3, 0x33); in broadwell_northbridge_early_init()
131 dm_pci_write_config8(dev, PAM4, 0x33); in broadwell_northbridge_early_init()
132 dm_pci_write_config8(dev, PAM5, 0x33); in broadwell_northbridge_early_init()
133 dm_pci_write_config8(dev, PAM6, 0x33); in broadwell_northbridge_early_init()
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| A D | pch.c | 49 dm_pci_write_config8(dev, ACPI_CNTL, ACPI_EN); in broadwell_pch_early_init()
51 dm_pci_write_config8(dev, GPIO_CNTL, GPIO_EN); in broadwell_pch_early_init()
213 dm_pci_write_config8(dev, 0xa9, 0x46); in pch_pm_init_magic()
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| /u-boot/board/imgtec/malta/ |
| A D | malta.c | 212 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10); in board_early_init_r()
213 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10); in board_early_init_r()
214 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11); in board_early_init_r()
215 dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11); in board_early_init_r()
235 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); in board_early_init_r()
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| /u-boot/drivers/pci/ |
| A D | pci_auto.c | 180 dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, in dm_pciauto_setup_device()
182 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); in dm_pciauto_setup_device()
369 dm_pci_write_config8(dev, PCI_PRIMARY_BUS, in dm_pciauto_prescan_setup_bridge()
371 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr)); in dm_pciauto_prescan_setup_bridge()
372 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); in dm_pciauto_prescan_setup_bridge()
425 dm_pci_write_config8(dev, PCI_IO_BASE, in dm_pciauto_prescan_setup_bridge()
435 dm_pci_write_config8(dev, PCI_IO_BASE, 0xf0 | io_32); in dm_pciauto_prescan_setup_bridge()
436 dm_pci_write_config8(dev, PCI_IO_LIMIT, 0x0 | io_32); in dm_pciauto_prescan_setup_bridge()
465 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr)); in dm_pciauto_postscan_setup_bridge()
508 dm_pci_write_config8(dev, PCI_IO_LIMIT, in dm_pciauto_postscan_setup_bridge()
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| A D | pci-uclass.c | 348 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value) in dm_pci_write_config8() function
493 return dm_pci_write_config8(dev, offset, val); in dm_pci_clrset_config8()
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| /u-boot/arch/x86/cpu/intel_common/ |
| A D | lpc.c | 28 dm_pci_write_config8(pch, 0xdc, reg8); in enable_spi_prefetch()
98 dm_pci_write_config8(dev, bios_ctrl, bios_cntl); in lpc_set_spi_protect()
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| /u-boot/arch/x86/cpu/apollolake/ |
| A D | punit.c | 50 dm_pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x2); in punit_init()
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| /u-boot/drivers/pch/ |
| A D | pch7.c | 36 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); in pch7_set_spi_protect()
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| /u-boot/drivers/sound/ |
| A D | ivybridge_sound.c | 79 dm_pci_write_config8(dev, 0x3c, 0xa); /* unused? */ in bd82x6x_azalia_probe()
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| /u-boot/arch/x86/cpu/ |
| A D | irq.c | 117 dm_pci_write_config8(dev->parent, in pirq_assign_irq()
327 dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80); in irq_enable_sci()
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| /u-boot/drivers/net/ |
| A D | dc2114x.c | 479 dm_pci_write_config8(dev, PCI_CFDA_PSM, WAKEUP); in dc2114x_start()
490 dm_pci_write_config8(dev, PCI_CFDA_PSM, SLEEP); in dc2114x_stop()
579 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x60); in dc2114x_probe()
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| A D | rtl8139.c | 642 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20); in rtl8139_probe()
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| A D | pcnet.c | 534 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20); in pcnet_probe()
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| A D | eepro100.c | 857 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20); in eepro100_probe()
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| /u-boot/arch/x86/lib/ |
| A D | bios_interrupts.c | 191 dm_pci_write_config8(dev, reg, byte); in int1a_handler()
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| /u-boot/drivers/i2c/ |
| A D | intel_i2c.c | 259 dm_pci_write_config8(dev, HOSTC, HST_EN); in intel_i2c_probe()
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| /u-boot/drivers/bios_emulator/ |
| A D | bios.c | 257 dm_pci_write_config8(_BE_env.vgaInfo.pcidev,
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| /u-boot/drivers/video/ |
| A D | ivybridge_igd.c | 697 dm_pci_write_config8(video_dev, MSAC, reg8); in sandybridge_setup_graphics()
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| /u-boot/include/ |
| A D | pci.h | 1099 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
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| /u-boot/drivers/ata/ |
| A D | ahci.c | 428 dm_pci_write_config8(dev, 0x41, 0xa1); in ahci_init_one()
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