Searched refs:emif (Results 1 – 17 of 17) sorted by relevance
| /u-boot/arch/arm/mach-omap2/ |
| A D | emif-common.c | 33 reg = readl(&emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()
37 writel(reg, &emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()
40 readl(&emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()
95 iodft = readl(&emif->emif_iodft_tlgc); in emif_reset_phy()
97 writel(iodft, &emif->emif_iodft_tlgc); in emif_reset_phy()
195 &emif->emif_l3_config); in emif_update_timings()
198 &emif->emif_l3_config); in emif_update_timings()
201 &emif->emif_l3_config); in emif_update_timings()
224 &emif->emif_ddr_phy_ctrl_1); in omap5_ddr3_leveling()
237 readl(&emif->emif_rd_wr_lvl_ctl); in omap5_ddr3_leveling()
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| A D | Makefile | 25 obj-y += emif-common.o
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| A D | clocks-common.c | 380 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; in setup_dplls() local
391 if (emif_sdram_type(readl(&emif->emif_sdram_config)) == in setup_dplls()
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| /u-boot/cmd/ti/ |
| A D | ddr3.c | 166 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; in ddr_check_ecc_status() local
167 u32 err_1b = readl(&emif->emif_1b_ecc_err_cnt); in ddr_check_ecc_status()
168 u32 int_status = readl(&emif->emif_irqstatus_raw_sys); in ddr_check_ecc_status()
193 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; in ddr_memory_ecc_err() local
194 u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); in ddr_memory_ecc_err()
203 writel(0, &emif->emif_ecc_ctrl_reg); in ddr_memory_ecc_err()
215 writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg); in ddr_memory_ecc_err()
243 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); in is_addr_valid()
244 range = readl(&emif->emif_ecc_address_range_1); in is_addr_valid()
260 range = readl(&emif->emif_ecc_address_range_2); in is_addr_valid()
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| /u-boot/arch/arm/mach-omap2/am33xx/ |
| A D | ti816x_emif4.c | 23 static void ddr_init_settings(const struct cmd_control *ctrl, int emif) in ddr_init_settings() argument
35 config_cmd_ctrl(ctrl, emif); in ddr_init_settings()
92 static void ddr3_sw_levelling(const struct ddr_data *data, int emif) in ddr3_sw_levelling() argument
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| /u-boot/arch/arm/mach-omap2/omap4/ |
| A D | Makefile | 9 obj-y += emif.o
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| /u-boot/arch/arm/include/asm/arch-am33xx/ |
| A D | hardware_ti816x.h | 56 #define DDRPHY_CONFIG_BASE ((emif == 0) ? \
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| /u-boot/arch/arm/mach-omap2/omap5/ |
| A D | Makefile | 8 obj-y += emif.o
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| A D | sdram.c | 514 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; in do_ext_phy_settings_omap5() local
517 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); in do_ext_phy_settings_omap5()
544 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; in do_ext_phy_settings_dra7() local
555 emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1); in do_ext_phy_settings_dra7()
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| A D | hwinit.c | 127 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; in do_io_settings() local
183 if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2) in do_io_settings()
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| /u-boot/tools/ |
| A D | ublimage.h | 75 uint32_t emif; /* member
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| /u-boot/arch/arm/dts/ |
| A D | omap4.dtsi | 256 emif1: emif@4c000000 {
257 compatible = "ti,emif-4d";
268 emif2: emif@4d000000 {
269 compatible = "ti,emif-4d";
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| A D | am33xx.dtsi | 594 emif: emif@4c000000 { label
595 compatible = "ti,emif-am3352";
597 ti,hwmods = "emif";
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| A D | am4372.dtsi | 129 emif: emif@4c000000 { label
130 compatible = "ti,emif-am4372";
132 ti,hwmods = "emif";
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| A D | k3-j721s2-ddr.dtsi | 17 emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>;
18 emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>;
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| A D | dra7xx-clocks.dtsi | 1001 emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
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| /u-boot/arch/arm/include/asm/ |
| A D | emif.h | 1257 struct emif_reg_struct *emif = (struct emif_reg_struct *)base; in get_emif_rev() local
1259 return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) in get_emif_rev()
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