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Searched refs:gcr (Results 1 – 23 of 23) sorted by relevance

/u-boot/arch/arm/mach-npcm/npcm8xx/
A Dreset.c22 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; in reset_misc() local
24 clrbits_le32(&gcr->intcr2, INTCR2_WDC); in reset_misc()
29 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; in npcm_get_reset_status() local
32 val = readl(&gcr->ressr); in npcm_get_reset_status()
34 val = readl(&gcr->intcr2); in npcm_get_reset_status()
A Dcpu.c38 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; in print_cpuinfo() local
44 val = readl(&gcr->mdlr); in print_cpuinfo()
63 val = readl(&gcr->pdid); in print_cpuinfo()
/u-boot/arch/arm/dts/
A Dnuvoton-common-npcm8xx.dtsi226 syscon = <&gcr>;
235 syscon = <&gcr>;
244 syscon = <&gcr>;
257 syscon = <&gcr>;
271 syscon = <&gcr>;
285 syscon = <&gcr>;
299 syscon = <&gcr>;
313 syscon = <&gcr>;
327 syscon = <&gcr>;
341 syscon = <&gcr>;
[all …]
A Dnuvoton-npcm7xx-u-boot.dtsi121 syscon-gcr = <&gcr>;
145 syscon = <&gcr>;
A Dnuvoton-common-npcm7xx.dtsi89 gcr: gcr@800000 { label
90 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
563 syscon-gcr = <&gcr>;
A Dnuvoton-npcm8xx-u-boot.dtsi158 syscon = <&gcr>;
441 syscon-gcr = <&gcr>;
/u-boot/arch/arm/mach-npcm/npcm7xx/
A Dcpu.c14 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; in print_cpuinfo() local
17 mdlr = readl(&gcr->mdlr); in print_cpuinfo()
36 id = readl(&gcr->pdid); in print_cpuinfo()
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dinterrupts.c39 out_be32(&pic->gcr, MPC85xx_PICGCR_RST); in interrupt_init_cpu()
40 while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) in interrupt_init_cpu()
42 out_be32(&pic->gcr, MPC85xx_PICGCR_M); in interrupt_init_cpu()
43 in_be32(&pic->gcr); in interrupt_init_cpu()
/u-boot/board/nuvoton/arbel_evb/
A Darbel_evb.c20 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; in dram_init() local
26 gd->ram_size = readl(&gcr->scrpad_b); in dram_init()
/u-boot/board/nuvoton/poleg_evb/
A Dpoleg_evb.c22 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; in dram_init() local
24 int ramsize = (readl(&gcr->intcr3) >> 8) & 0x7; in dram_init()
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun50i_h6.c351 writel(0x0, &mctl_phy->dx[2].gcr[0]); in mctl_com_init()
352 writel(0x0, &mctl_phy->dx[3].gcr[0]); in mctl_com_init()
442 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800); in mctl_channel_init()
444 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555); in mctl_channel_init()
446 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010); in mctl_channel_init()
507 writel(0x00000909, &mctl_phy->dx[i].gcr[5]); in mctl_channel_init()
514 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val); in mctl_channel_init()
520 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val); in mctl_channel_init()
529 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff); in mctl_channel_init()
A Ddram_sun9i.c694 debug("DX2GCR0 reset: 0x%x\n", readl(&mctl_phy->dx[2].gcr[0])); in mctl_channel_init()
695 writel(0x7C000285, &mctl_phy->dx[2].gcr[0]); in mctl_channel_init()
696 writel(0x7C000285, &mctl_phy->dx[3].gcr[0]); in mctl_channel_init()
709 clrbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff); in mctl_channel_init()
710 clrbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
717 clrsetbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff, in mctl_channel_init()
720 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
723 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
A Ddram_sunxi_dw.c516 clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask); in mctl_channel_init()
556 writel(0x0, &mctl_ctl->dx[2].gcr); in mctl_channel_init()
557 writel(0x0, &mctl_ctl->dx[3].gcr); in mctl_channel_init()
559 writel(0x0, &mctl_ctl->dx[1].gcr); in mctl_channel_init()
611 writel(0x0, &mctl_ctl->dx[2].gcr); in mctl_channel_init()
612 writel(0x0, &mctl_ctl->dx[3].gcr); in mctl_channel_init()
617 writel(0x0, &mctl_ctl->dx[1].gcr); in mctl_channel_init()
/u-boot/arch/arm/include/asm/arch-imx8ulp/
A Dimx-regs.h81 u32 gcr; member
/u-boot/arch/arm/include/asm/arch-imx9/
A Dimx-regs.h68 u32 gcr; member
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sunxi_dw.h140 u32 gcr; /* 0x44 general configuration register */ member
A Ddram_sun9i.h146 u32 gcr[4]; /* DATX8 general configuration register */ member
A Ddram_sun50i_h6.h245 u32 gcr[7]; /* 0x00 */ member
/u-boot/drivers/i2c/
A Dnpcm_i2c.c562 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; in npcm_i2c_probe() local
592 writel(i2csegctl_val, &gcr->i2csegctl); in npcm_i2c_probe()
/u-boot/arch/arm/include/asm/arch-omap3/
A Dcpu.h253 u32 gcr; member
/u-boot/drivers/clk/stm32/
A Dclk-stm32h7.c168 u32 gcr; /* 0xa0 Global Control Register */ member
/u-boot/arch/powerpc/include/asm/
A Dimmap_83xx.h414 u32 gcr; member
A Dimmap_85xx.h640 u32 gcr; /* Global Configuration */ member

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