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Searched refs:gpll0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-snapdragon/
A Dclock-snapdragon.c34 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) in clk_enable_gpll0() argument
36 if (readl(base + gpll0->status) & gpll0->status_bit) in clk_enable_gpll0()
39 setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); in clk_enable_gpll0()
41 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) in clk_enable_gpll0()
A Dclock-snapdragon.h39 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);

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