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Searched refs:iobase (Results 1 – 25 of 79) sorted by relevance

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/u-boot/drivers/net/
A Dravb.c132 void __iomem *iobase; member
353 eth->iobase + RAVB_REG_MAHR); in ravb_write_hwaddr()
388 writel(0, eth->iobase + RAVB_REG_RIC0); in ravb_dmac_init()
389 writel(0, eth->iobase + RAVB_REG_RIC1); in ravb_dmac_init()
390 writel(0, eth->iobase + RAVB_REG_RIC2); in ravb_dmac_init()
391 writel(0, eth->iobase + RAVB_REG_TIC); in ravb_dmac_init()
508 void __iomem *iobase; in ravb_probe() local
511 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE); in ravb_probe()
512 eth->iobase = iobase; in ravb_probe()
566 unmap_physmem(eth->iobase, MAP_NOCACHE); in ravb_probe()
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A Dsni_ave.c144 phys_addr_t iobase; member
191 return readl(priv->iobase + addr); in ave_desc_read()
215 writel(val, priv->iobase + addr); in ave_desc_write()
288 priv->iobase + AVE_MDIOCTR); in ave_mdiobus_write()
422 val = readl(priv->iobase + AVE_GRR); in ave_stop()
430 writel(0, priv->iobase + AVE_DESCC); in ave_stop()
459 writel(0, priv->iobase + AVE_GRR); in ave_reset()
511 priv->iobase + AVE_RXCR); in ave_start()
527 priv->iobase + AVE_RXMAC1R); in ave_write_hwaddr()
761 pdata->iobase = dev_read_addr(dev); in ave_of_to_plat()
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A Dpcnet.c88 void __iomem *iobase; member
103 writew(index, lp->iobase + PCNET_RAP); in pcnet_read_csr()
104 return readw(lp->iobase + PCNET_RDP); in pcnet_read_csr()
110 writew(val, lp->iobase + PCNET_RDP); in pcnet_write_csr()
116 return readw(lp->iobase + PCNET_BDP); in pcnet_read_bcr()
122 writew(val, lp->iobase + PCNET_BDP); in pcnet_write_bcr()
127 readw(lp->iobase + PCNET_RESET); in pcnet_reset()
132 writew(88, lp->iobase + PCNET_RAP); in pcnet_check()
509 u32 iobase; in pcnet_probe() local
513 iobase &= ~0xf; in pcnet_probe()
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A Dks8851_mll.c31 phys_addr_t iobase; member
48 writew(offset | (BE0 << shift_bit), ks->iobase + 2); in ks_rdreg8()
50 return (u8)(readw(ks->iobase) >> shift_data); in ks_rdreg8()
55 writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2); in ks_rdreg16()
57 return readw(ks->iobase); in ks_rdreg16()
62 writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2); in ks_wrreg16()
63 writew(val, ks->iobase); in ks_wrreg16()
78 *wptr++ = readw(ks->iobase); in ks_inblk()
92 writew(*wptr++, ks->iobase); in ks_outblk()
600 pdata->iobase = dev_read_addr(dev); in ks8851_of_to_plat()
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A Dsmc911x.c25 phys_addr_t iobase; member
52 return readl(priv->iobase + offset); in smc911x_reg_read()
54 return (readw(priv->iobase + offset) & 0xffff) | in smc911x_reg_read()
55 (readw(priv->iobase + offset + 2) << 16); in smc911x_reg_read()
61 writel(val, priv->iobase + offset); in smc911x_reg_write()
63 writew(val & 0xffff, priv->iobase + offset); in smc911x_reg_write()
64 writew(val >> 16, priv->iobase + offset + 2); in smc911x_reg_write()
462 pdata->iobase = dev_read_addr(dev); in smc911x_of_to_plat()
463 priv->iobase = pdata->iobase; in smc911x_of_to_plat()
A Dftgmac100.c79 struct ftgmac100 *iobase; member
106 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_mdio_read()
135 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_mdio_write()
187 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_phy_adjust_link()
250 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_reset()
266 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_set_mac()
284 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_get_mac()
306 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_stop()
320 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_start()
555 pdata->iobase = dev_read_addr(dev); in ftgmac100_of_to_plat()
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A Dxilinx_axi_mrmac.c46 struct mrmac_regs *regs = priv->iobase; in axi_mrmac_ethernet_init()
93 writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase + in axi_mrmac_ethernet_init()
95 writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase + in axi_mrmac_ethernet_init()
97 writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase + in axi_mrmac_ethernet_init()
100 ret = wait_for_bit_le32((u32 *)((phys_addr_t)priv->iobase + in axi_mrmac_ethernet_init()
165 struct mrmac_regs *regs = priv->iobase; in axi_mrmac_start()
475 priv->iobase = (struct mrmac_regs *)pdata->iobase; in axi_mrmac_probe()
519 pdata->iobase = dev_read_addr(dev); in axi_mrmac_of_to_plat()
A Dxilinx_axi_emac.c125 struct axi_regs *iobase; member
234 struct axi_regs *regs = priv->iobase; in phyread()
260 struct axi_regs *regs = priv->iobase; in phywrite()
290 struct axi_regs *regs = priv->iobase; in axiemac_phy_init()
390 struct axi_regs *regs = priv->iobase; in setup_phy()
477 struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase; in xxv_axi_ethernet_init()
489 struct axi_regs *regs = priv->iobase; in axi_ethernet_init()
540 struct axi_regs *regs = priv->iobase; in axiemac_write_hwaddr()
635 struct axi_regs *regs = priv->iobase; in axiemac_start()
832 priv->iobase = (struct axi_regs *)pdata->iobase; in axi_emac_probe()
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A Deepro100.c209 void __iomem *iobase; member
218 return le16_to_cpu(readw(addr + priv->iobase)); in INW()
223 writew(cpu_to_le16(command), addr + priv->iobase); in OUTW()
228 writel(cpu_to_le32(command), addr + priv->iobase); in OUTL()
234 return le32_to_cpu(readl(addr + priv->iobase)); in INL()
833 u32 iobase; in eepro100_probe() local
836 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); in eepro100_probe()
837 iobase &= ~0xf; in eepro100_probe()
839 debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", iobase); in eepro100_probe()
843 priv->iobase = (void __iomem *)bus_to_phys(dev, iobase); in eepro100_probe()
A Ddc2114x.c102 void __iomem *iobase; member
109 return le32_to_cpu(readl(priv->iobase + addr)); in dc2114x_inl()
114 writel(cpu_to_le32(command), priv->iobase + addr); in dc2114x_outl()
560 u32 iobase; in dc2114x_probe() local
562 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase); in dc2114x_probe()
563 iobase &= ~0xf; in dc2114x_probe()
565 debug("dc2114x: DEC 2114x PCI Device @0x%x\n", iobase); in dc2114x_probe()
569 priv->iobase = (void __iomem *)dm_pci_mem_to_phys(dev, iobase); in dc2114x_probe()
A Dfsl_mcdmafec.c84 volatile fecdma_t *fecp = (fecdma_t *)info->iobase; in fec_halt()
122 volatile fecdma_t *fecp = (fecdma_t *)info->iobase; in dbg_fec_regs()
235 volatile fecdma_t *fecp = (fecdma_t *)info->iobase; in fec_init()
240 printf("fec_init: iobase 0x%08x ...\n", info->iobase); in fec_init()
409 volatile fecdma_t *fecp = (fecdma_t *)info->iobase; in mcdmafec_recv()
499 info->iobase = pdata->iobase; in mcdmafec_probe()
500 info->miibase = pdata->iobase; in mcdmafec_probe()
566 pdata->iobase = dev_read_addr(dev); in mcdmafec_of_to_plat()
/u-boot/drivers/tpm/
A Dtpm2_tis_mmio.c31 void __iomem *iobase; member
40 *result++ = ioread8(drv_data->iobase + addr); in mmio_read_bytes()
51 iowrite8(*value++, drv_data->iobase + addr); in mmio_write_bytes()
60 *result = ioread32(drv_data->iobase + addr); in mmio_read32()
69 iowrite32(value, drv_data->iobase + addr); in mmio_write32()
97 drv_data->iobase = ioremap(ioaddr, sz); in tpm_tis_probe()
113 iounmap(drv_data->iobase); in tpm_tis_probe()
125 iounmap(drv_data->iobase); in tpm_tis_remove()
/u-boot/drivers/misc/
A Dsmsc_sio1007.c29 void sio1007_enable_serial(int port, int num, int iobase, int irq) in sio1007_enable_serial() argument
40 sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2); in sio1007_enable_serial()
44 sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2); in sio1007_enable_serial()
52 void sio1007_enable_runtime(int port, int iobase) in sio1007_enable_runtime() argument
58 sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4); in sio1007_enable_runtime()
59 sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12); in sio1007_enable_runtime()
A Dwinbond_w83627.c31 void winbond_enable_serial(uint dev, uint iobase, uint irq) in winbond_enable_serial() argument
36 pnp_set_iobase(dev, PNP_IDX_IO0, iobase); in winbond_enable_serial()
A Dsmsc_lpc47m.c24 void lpc47m_enable_serial(uint dev, uint iobase, uint irq) in lpc47m_enable_serial() argument
29 pnp_set_iobase(dev, PNP_IDX_IO0, iobase); in lpc47m_enable_serial()
/u-boot/arch/x86/lib/
A Dpinctrl_ich6.c63 static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node) in ich6_pinctrl_cfg_pin() argument
107 if (iobase != -1) { in ich6_pinctrl_cfg_pin()
122 iobase_addr = iobase + pad_offset; in ich6_pinctrl_cfg_pin()
160 u32 iobase = -1; in ich6_pinctrl_probe() local
183 ret = pch_get_io_base(pch, &iobase); in ich6_pinctrl_probe()
185 debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase); in ich6_pinctrl_probe()
193 ret = ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node); in ich6_pinctrl_probe()
/u-boot/drivers/spi/
A Dnxp_fspi.c341 void __iomem *iobase; member
475 reg = fspi_readl(f, f->iobase + FSPI_MCR0); in nxp_fspi_invalid()
487 void __iomem *base = f->iobase; in nxp_fspi_prepare_lut()
638 void __iomem *base = f->iobase; in nxp_fspi_fill_txfifo()
682 void __iomem *base = f->iobase; in nxp_fspi_read_rxfifo()
732 void __iomem *base = f->iobase; in nxp_fspi_do_op()
864 void __iomem *base = f->iobase; in nxp_fspi_default_setup()
911 reg = fspi_readl(f, f->iobase + FSPI_MCR2); in nxp_fspi_default_setup()
996 fdt_addr_t iobase; in nxp_fspi_of_to_plat() local
1004 if (iobase == FDT_ADDR_T_NONE) { in nxp_fspi_of_to_plat()
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A Dfsl_qspi.c273 void __iomem *iobase; member
411 void __iomem *base = q->iobase; in fsl_qspi_prepare_lut()
495 reg = qspi_readl(q, q->iobase + QUADSPI_MCR); in fsl_qspi_invalidate()
497 qspi_writel(q, reg, q->iobase + QUADSPI_MCR); in fsl_qspi_invalidate()
550 void __iomem *base = q->iobase; in fsl_qspi_fill_txfifo()
575 void __iomem *base = q->iobase; in fsl_qspi_read_rxfifo()
606 void __iomem *base = q->iobase; in fsl_qspi_do_op()
633 void __iomem *base = q->iobase; in fsl_qspi_exec_op()
708 void __iomem *base = q->iobase; in fsl_qspi_default_setup()
743 q->iobase + QUADSPI_BFGENCR); in fsl_qspi_default_setup()
[all …]
/u-boot/test/dm/
A Dpch.c18 u32 gbase, iobase; in dm_test_pch_base() local
32 ut_assertok(pch_get_io_base(dev, &iobase)); in dm_test_pch_base()
33 ut_asserteq(0x30, iobase); in dm_test_pch_base()
/u-boot/arch/x86/include/asm/
A Dpnp_def.h67 static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase) in pnp_set_iobase() argument
69 pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); in pnp_set_iobase()
70 pnp_write_config(dev, index + 1, iobase & 0xff); in pnp_set_iobase()
/u-boot/drivers/clk/
A Dclk_pic32.c91 void __iomem *iobase; member
100 v = readl(priv->iobase + SPLLCON); in pic32_get_pll_rate()
126 v = readl(priv->iobase + OSCCON); in pic32_get_sysclk()
162 reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10; in pic32_get_pbclk()
197 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; in pic32_set_refclk()
241 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; in pic32_get_refclk()
404 priv->iobase = ioremap(addr, size); in pic32_clk_probe()
405 if (!priv->iobase) in pic32_clk_probe()
/u-boot/include/
A Dsmsc_sio1007.h72 void sio1007_enable_serial(int port, int num, int iobase, int irq);
81 void sio1007_enable_runtime(int port, int iobase);
/u-boot/drivers/rtc/
A Dmvrtc.c137 struct mvrtc_registers *regs = (struct mvrtc_registers *)pdata->iobase; in mv_rtc_get()
145 struct mvrtc_registers *regs = (struct mvrtc_registers *)pdata->iobase; in mv_rtc_set()
153 struct mvrtc_registers *regs = (struct mvrtc_registers *)pdata->iobase; in mv_rtc_reset()
175 pdata->iobase = dev_read_addr(dev); in mv_rtc_of_to_plat()
/u-boot/board/freescale/ls1012afrdm/
A Deth.c95 .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
107 .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
/u-boot/board/freescale/ls1012ardb/
A Deth.c141 .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
153 .iobase = (phys_addr_t)EMAC2_BASE_ADDR,

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