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Searched refs:isb (Results 1 – 25 of 41) sorted by relevance

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/u-boot/arch/arm/cpu/armv8/
A Dtlb.S22 isb
26 isb
30 isb
A Dgeneric_timer.c43 isb(); in timer_read_counter()
70 isb(); in timer_read_counter()
85 isb(); in timer_read_counter()
A Dstart.S147 4: isb
160 isb
230 isb
245 isb
253 isb
263 isb
274 isb
282 isb
A Dcache.S29 isb /* sync change of cssidr_el1 */
98 isb
216 isb sy
253 0: isb
268 0: isb
277 0: isb
A Dfel_utils.S57 isb sy
61 isb sy
/u-boot/arch/arm/lib/
A Dgic_64.S101 isb
119 isb
123 isb
126 isb
132 isb
135 isb
139 isb
178 isb
/u-boot/arch/arm/include/asm/arch-armv7/
A Dgenerictimer.h36 isb
39 1 : isb
45 isb
/u-boot/arch/arm/cpu/armv7m/
A Dcache.c167 isb(); /* Make sure instruction stream sees it */ in action_cache_range()
199 isb(); /* Make sure instruction stream sees it */ in action_dcache_all()
218 isb(); /* Make sure instruction stream sees it */ in dcache_enable()
236 isb(); /* Make sure instruction stream sees it */ in dcache_disable()
313 isb(); /* Make sure instruction stream sees it */ in invalidate_icache_all()
326 isb(); /* Make sure instruction stream sees it */ in icache_enable()
339 isb(); /* flush pipeline */ in icache_disable()
341 isb(); /* subsequent instructions fetch see cache disable effect */ in icache_disable()
A Dmpu.c29 isb(); /* Make sure instruction stream sees it */ in enable_mpu()
/u-boot/arch/arm/mach-mediatek/mt7629/
A Dlowlevel_init.S35 isb
38 isb
40 isb
/u-boot/arch/arm/cpu/armv7/
A Dmpu_v7r.c43 isb(); in disable_mpu()
54 isb(); in enable_mpu()
A Dnonsec_virt.S49 isb
64 isb
71 isb
88 isb
202 isb
A Dcache_v7_asm.S40 isb @ isb to sych the new cssr&csidr
71 isb
110 isb @ isb to sych the new cssr&csidr
141 isb
A Dcache_v7.c94 isb(); in v7_inval_tlb()
198 isb(); in invalidate_icache_all()
A Dpsci.S141 isb
185 isb @ isb to sych the new cssr&csidr
213 isb
222 isb
231 isb
245 isb
/u-boot/arch/arm/cpu/armv7/sunxi/
A Dpsci.c67 isb(); in __mdelay()
71 isb(); in __mdelay()
76 isb(); in __mdelay()
207 isb(); in cp15_write_scr()
/u-boot/arch/arm/mach-imx/mx7/
A Dpsci-suspend.S48 isb
62 isb
/u-boot/arch/arm/include/asm/
A Dcache.h27 isb(); in invalidate_l2_cache()
A Dbarriers.h46 #define isb() ISB macro
A Darmv7.h81 isb(); in write_l2ctlr()
/u-boot/arch/arm/mach-zynq/
A Dlowlevel_init.S17 isb
/u-boot/arch/arm/mach-socfpga/
A Dtimer_s10.c35 isb(); in __get_time_stamp()
/u-boot/arch/arm/mach-sunxi/
A Drmr_switch.S41 isb sy
45 isb sy
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dlowlevel.S224 isb
286 isb
304 isb
/u-boot/arch/arm/mach-orion5x/include/mach/
A Dcpu.h197 isb(); in writefr_extra_feature_reg()

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