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Searched refs:ldr (Results 1 – 25 of 89) sorted by relevance

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/u-boot/board/freescale/mx7ulp_evk/
A Dplugin.S10 ldr r2, =0x403f0000
11 ldr r3, =0x00000000
14 ldr r2, =0x403e0000
15 ldr r3, =0x01000020
17 ldr r3, =0x01000000
20 ldr r3, =0x80808080
22 ldr r3, =0x00160002
24 ldr r3, =0x00000001
26 ldr r3, =0x00000014
28 ldr r3, =0x00000001
[all …]
/u-boot/board/freescale/mx6ullevk/
A Dplugin.S11 ldr r1, =0x000C0000
13 ldr r1, =0x00000000
15 ldr r1, =0x00000030
17 ldr r1, =0x00000030
21 ldr r1, =0x000C0030
24 ldr r1, =0x00000000
27 ldr r1, =0x00000030
32 ldr r1, =0x00020000
35 ldr r1, =0x00000030
37 ldr r1, =0x00000030
[all …]
/u-boot/board/freescale/mx6sllevk/
A Dplugin.S11 ldr r1, =0x00080000
13 ldr r1, =0x00000000
15 ldr r1, =0x00000030
19 ldr r1, =0x00020000
21 ldr r1, =0x00003030
27 ldr r1, =0x00020000
29 ldr r1, =0x00000030
39 ldr r1, =0x00082030
43 ldr r1, =0x00008000
45 ldr r1, =0xA1390003
[all …]
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dlowlevel.S40 ldr w2, [x2]
50 ldr w2, [x2]
85 ldr x1, =0x00000010
101 ldr x1, =0x00000020
104 ldr x1, =0x00000020
117 ldr x1, =0x00FF000C
179 ldr x1, =SMMU_BASE
193 ldr x0, =GICR_BASE
354 ldr w0, [x1]
368 ldr x2, [x0]
[all …]
/u-boot/board/samsung/goni/
A Dlowlevel_init.S34 ldr r0, [r2]
46 ldr r1, [r0]
87 ldr r1, [r0]
153 ldr r1, [r0]
168 ldr r1, =0x9
202 ldr r1, [r0]
208 ldr r1, [r0]
220 ldr r1, [r0]
226 ldr r1, [r0]
292 ldr r1, =0xf
[all …]
/u-boot/arch/arm/mach-imx/mx5/
A Dlowlevel_init.S63 ldr r1, =0x77777777
84 ldr r1, =0x00000203
89 ldr r1, =0x00120125
92 ldr r1, =0x001901A3
99 ldr r0, =\pll
109 ldr r1, =0x00001232
126 ldr r1, =0x00001232
136 ldr r2, =\pll
138 ldr r1, =0x00001236
144 ldr r5, \freq
[all …]
/u-boot/board/samsung/smdkc100/
A Dlowlevel_init.S25 ldr r8, =S5PC100_GPIO_BASE
34 ldr r1, =0x9
76 ldr r1, =0x00011110
78 ldr r1, =0x1
80 ldr r1, =0x00011301
100 ldr r1, =0x80600603
125 ldr r1, =0x22222222
127 ldr r1, =0x00022222
136 ldr r0, =0xE3800000
143 ldr r0, =0xE2800000
[all …]
/u-boot/arch/arm/mach-uniphier/arm32/
A Ddebug_ll.S26 ldr \rd, [\ra]
34 ldr r1, [r0]
43 ldr r0, =(SG_BASE + SG_IECTRL)
44 ldr r1, [r0]
67 ldr r1, [r0]
82 ldr r1, [r0]
108 ldr r1, [r0]
123 ldr r1, [r0]
133 ldr r1, [r0]
148 ldr r1, [r0]
[all …]
/u-boot/arch/arm/mach-orion5x/
A Dlowlevel_init.S79 ldr r3, =0xD0000000
87 ldr r0, =0x00000001
94 ldr r0, =0x00000030
108 ldr r0, =SDRAM_CONFIG
150 ldr r0, [r3, #0x418]
155 ldr r0, =SDRAM_MODE
164 ldr r0, [r3, #0x418]
169 ldr r0, [r3, #0x4C0]
244 ldr r3, =0x10000
267 ldr r0, =0
[all …]
/u-boot/arch/arm/mach-aspeed/ast2600/
A Dlowlevel_init.S56 ldr r1, =SCU_PROT_KEY1
58 ldr r1, =SCU_PROT_KEY2
63 ldr r1, =SCU_HWSTRAP1
64 ldr r1, [r1]
132 ldr r0, [r0]
149 ldr r0, =SCU_MMIO_DEC
163 ldr r0, =SCU_HWSTRAP1
164 ldr r1, [r0]
186 ldr r3, [r0], #0x4
222 ldr r4, [r0]
[all …]
/u-boot/arch/arm/mach-at91/arm926ejs/
A Dlowlevel_init.S38 ldr r0, =SMRDATA
39 ldr r2, =SMRDATA1
44 ldr r1, [r0], #4
46 ldr r3, [r0], #4
58 ldr r0, [r1]
76 ldr r3, [r2]
94 ldr r3, [r2]
114 ldr r3, [r2]
125 ldr r3, [r2]
136 ldr r1, [r0]
[all …]
/u-boot/arch/arm/lib/
A Dcrt0.S69 ldr r0, =__bss_start /* this is auto-relocated! */
72 ldr r3, =__bss_end /* this is auto-relocated! */
78 ldr r1, =__bss_end /* this is auto-relocated! */
104 ldr r0, =(CONFIG_TPL_STACK)
106 ldr r0, =(CONFIG_SPL_STACK)
108 ldr r0, =(SYS_INIT_SP_ADDR)
140 ldr r9, [r9, #GD_NEW_GD] /* r9 <- gd->new_gd */
145 ldr r1, _start_ofs
147 ldr r1, =CONFIG_TEXT_BASE
151 ldr r0, [r9, #GD_ENV_ADDR] /* r0 = gd->env_addr */
[all …]
A Dcrt0_64.S73 ldr x0, =(CONFIG_TPL_STACK)
75 ldr x0, =(CONFIG_SPL_STACK)
85 ldr x0, =(SYS_INIT_SP_ADDR)
110 ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */
113 ldr x0, [x18, #GD_FLAGS] /* x0 <- gd->flags */
121 ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */
125 ldr x0, [x18, #GD_ENV_ADDR] /* x0 <- gd->env_addr */
131 ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */
163 ldr x0, =__bss_start /* this is auto-relocated! */
164 ldr x1, =__bss_end /* this is auto-relocated! */
[all …]
A Drelocate.S34 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
35 ldr r1, =V7M_SCB_BASE
43 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
52 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
82 ldr r1, _image_copy_start_ofs
86 ldr r1, _image_copy_start_ofs
88 ldr r2, _image_copy_end_ofs
99 ldr r1, _rel_dyn_start_ofs
101 ldr r1, _rel_dyn_end_ofs
111 ldr r1, [r0]
/u-boot/arch/arm/include/asm/arch-mx7/
A Dmx7_plugin.S24 ldr r0, =0x30384680
25 ldr r1, [r0]
29 ldr r0, =0x30B10158
30 ldr r1, [r0]
57 ldr r3, =ROM_VERSION_OFFSET
58 ldr r4, [r3]
59 ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
60 ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
72 ldr r5, boot_data2
74 ldr r5, image_len2
[all …]
/u-boot/arch/arm/include/asm/arch-mx6/
A Dmx6_plugin.S46 ldr r3, =ROM_VERSION_OFFSET
47 ldr r4, [r3]
50 ldr r3, =0x00900b00
51 ldr r4, =0x50000000
54 ldr r3, =0x00900800
55 ldr r4, =0x08000000
65 ldr r4, [r3]
67 ldr r3, =ROM_VERSION_TO12
72 ldr r3, =ROM_VERSION_TO15
116 ldr r5, boot_data2
[all …]
/u-boot/arch/arm/mach-lpc32xx/
A Dlowlevel_init.S22 ldr r0, =0x0000003D
23 ldr r1, =0x40004040
27 ldr r0, =0x0001401E
28 ldr r1, =0x40004058
33 ldr r0, [r1]
38 ldr r1, =0x40004044
39 ldr r0, [r1]
/u-boot/arch/arm/mach-socfpga/
A Dlowlevel_init_soc64.S18 ldr x4, =CPU_RELEASE_ADDR
19 ldr x5, [x4]
27 ldr x0, =GICD_BASE
31 ldr x0, =GICR_BASE
34 ldr x0, =GICD_BASE
35 ldr x1, =GICC_BASE
50 ldr x0, =GICC_BASE
59 ldr x5, =ES_TO_AARCH64
65 ldr x5, =ES_TO_AARCH64
/u-boot/arch/arm/mach-at91/arm920t/
A Dlowlevel_init.S48 ldr r0, =SMRDATA
49 ldr r1, _MTEXT_BASE
51 ldr r2, =SMRDATAE
55 ldr r1, [r0], #4
57 ldr r3, [r0], #4
62 ldr r0, =0x00010000
67 ldr r0, =SMRDATA1
68 ldr r1, _MTEXT_BASE
70 ldr r2, =SMRDATA1E
74 ldr r1, [r0], #4
[all …]
/u-boot/arch/arm/mach-aspeed/ast2500/
A Dlowlevel_init.S18 ldr r0, =SCU_PROT_KEY
19 ldr r1, =SCU_UNLOCK_VALUE
23 ldr r0, =SCU_VGA_HANDSHAKE
24 ldr r1, [r0]
29 ldr r0, =SCU_HW_STRAP
30 ldr r1, [r0]
37 ldr r0, =WDT3_CTRL
/u-boot/board/cortina/presidio-asic/
A Dlowlevel_init.S30 ldr x0, =CFG_SYS_TIMER_BASE
37 ldr x0, =GICD_BASE
41 ldr x0, =GICR_BASE
44 ldr x0, =GICD_BASE
45 ldr x1, =GICC_BASE
60 ldr x0, =GICC_BASE
69 ldr x5, =ES_TO_AARCH64
75 ldr x5, =ES_TO_AARCH64
/u-boot/arch/arm/mach-s5pc1xx/
A Dreset.S14 ldr r1, =S5PC100_PRO_ID
15 ldr r2, [r1]
16 ldr r4, =0x00010000
21 ldr r1, =S5PC100_SWRESET
22 ldr r2, =0xC100
25 ldr r1, =S5PC110_SWRESET
/u-boot/arch/arm/mach-rmobile/
A Dlowlevel_init_gen3.S47 ldr x0, =GICD_BASE
54 ldr x0, =GICD_BASE
58 ldr x0, =GICR_BASE
61 ldr x0, =GICD_BASE
62 ldr x1, =GICC_BASE
76 ldr x0, =GICC_BASE
85 ldr x5, =ES_TO_AARCH64
91 ldr x5, =ES_TO_AARCH64
A Dlowlevel_init.S12 ldr r0, =MERAM_BASE
26 ldr r1, =ICCICR
32 ldr r1, =ICCICR
40 ldr r2, [r1, #0xC]
43 ldr r0, =MERAM_BASE
44 ldr r2, [r0]
62 ldr sp, MERAM_STACK
/u-boot/arch/arm/include/asm/arch-mx7ulp/
A Dmx7ulp_plugin.S40 ldr r3, =ROM_VERSION_OFFSET
41 ldr r4, [r3]
42 ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
43 ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
55 ldr r5, boot_data2
57 ldr r5, image_len2
59 ldr r5, second_ivt_offset

Completed in 76 milliseconds

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