Searched refs:max_rate (Results 1 – 6 of 6) sorted by relevance
| /u-boot/drivers/clk/ti/ |
| A D | clk-am3-dpll.c | 23 ulong max_rate; member
37 ulong max_rate; member
50 if (priv->max_rate && rate > priv->max_rate) { in clk_ti_am3_dpll_round_rate()
52 rate, priv->max_rate); in clk_ti_am3_dpll_round_rate()
53 rate = priv->max_rate; in clk_ti_am3_dpll_round_rate()
333 priv->max_rate = data->max_rate; in clk_ti_am3_dpll_of_to_plat()
383 .max_rate = 1000000000
387 .max_rate = 2000000000
391 .max_rate = 1000000000
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| /u-boot/drivers/clk/imx/ |
| A D | clk-pllv3.c | 172 unsigned long max_rate; in clk_pllv3_sys_set_rate() local
179 max_rate = parent_rate * 108 / 2; in clk_pllv3_sys_set_rate()
181 if (rate < min_rate || rate > max_rate) in clk_pllv3_sys_set_rate()
227 unsigned long max_rate; in clk_pllv3_av_set_rate() local
237 max_rate = parent_rate * 54; in clk_pllv3_av_set_rate()
239 if (rate < min_rate || rate > max_rate) in clk_pllv3_av_set_rate()
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| /u-boot/drivers/phy/rockchip/ |
| A D | phy-rockchip-inno-dsidphy.c | 207 enum phy_max_rate max_rate; member
403 if (inno->pdata->max_rate == MAX_2_5GHZ) { in inno_dsidphy_mipi_mode_enable()
480 if (inno->pdata->max_rate == MAX_1GHZ) { in inno_dsidphy_mipi_mode_enable()
504 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_dsidphy_mipi_mode_enable()
511 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_dsidphy_mipi_mode_enable()
516 if (inno->pdata->max_rate == MAX_2_5GHZ) in inno_dsidphy_mipi_mode_enable()
611 .max_rate = MAX_1GHZ,
617 .max_rate = MAX_2_5GHZ,
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| /u-boot/include/fsl-mc/ |
| A D | fsl_dpmac.h | 48 MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\
251 uint32_t max_rate; member
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| A D | fsl_dprc.h | 365 MC_CMD_OP(cmd, 4, 0, 32, uint32_t, cfg->max_rate); \
883 uint32_t max_rate; member
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| /u-boot/drivers/net/ldpaa_eth/ |
| A D | ldpaa_eth.c | 812 .max_rate = 0 in ldpaa_dpmac_bind()
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