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Searched refs:mode_offset (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/clk/rockchip/
A Dclk_pll.c271 rk_clrsetreg(base + pll->mode_offset, in rk3036_pll_set_rate()
307 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
313 readl(base + pll->mode_offset)); in rk3036_pll_set_rate()
325 con = readl(base + pll->mode_offset); in rk3036_pll_get_rate()
408 rk_clrsetreg(base + pll->mode_offset, in rk3588_pll_set_rate()
452 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3588_pll_set_rate()
499 readl(base + pll->mode_offset)); in rk3588_pll_set_rate()
511 con = readl(base + pll->mode_offset); in rk3588_pll_get_rate()
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dclock.h53 .mode_offset = _mode, \
113 unsigned int mode_offset; member
/u-boot/lib/
A Dtpm-v1.c40 const size_t mode_offset = 10; in tpm1_startup() local
45 mode_offset, mode)) in tpm1_startup()

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