| /u-boot/board/ti/ks2_evm/ |
| A D | ddr3_k2g.c | 31 .mr1 = 0x00000006ul,
71 .mr1 = 0x00000006ul,
132 .mr1 = 0x00000006ul,
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| A D | ddr3_cfg.c | 29 .mr1 = 0x00000006ul,
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| /u-boot/board/imgtec/ci20/ |
| A D | ci20.c | 292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a23.c | 40 .mr1 = 4,
117 writel(dram_para.mr1, &mctl_phy->mr1); in mctl_init()
202 writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); in mctl_init()
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| A D | dram_sun8i_a83t.c | 137 writel(MCTL_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
142 writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
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| A D | dram_sun8i_a33.c | 136 writel(MCTL_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
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| A D | dram_sun6i.c | 125 writel(MCTL_MR1, &mctl_phy->mr1); in mctl_channel_init()
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| A D | dram_sun9i.c | 635 writel(mr[1], &mctl_phy->mr1); in mctl_channel_init()
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| /u-boot/arch/arm/mach-keystone/include/mach/ |
| A D | ddr3.h | 29 unsigned int mr1; member
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sun8i_a23.h | 25 u32 mr1; member
185 u32 mr1; /* 0x58 mode register 1 */ member
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| A D | dram_sun8i_a33.h | 79 u32 mr1; /* 0x34 */ member
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| A D | dram_sun8i_a83t.h | 79 u32 mr1; /* 0x34 */ member
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| A D | dram_sun9i.h | 112 u32 mr1; /* 0xa0 mode register 1 */ member
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| A D | dram_sun6i.h | 178 u32 mr1; /* 0x44 mode register 1 */ member
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| /u-boot/drivers/ram/stm32mp1/ |
| A D | stm32mp1_ddr.h | 138 u32 mr1; member
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| A D | stm32mp1_ddr_regs.h | 160 u32 mr1; /* 0x44 Mode 1*/ member
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| A D | stm32mp1_ddr.c | 177 DDRPHY_REG_TIMING(mr1),
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| /u-boot/arch/arm/mach-omap2/omap4/ |
| A D | sdram_elpida.c | 309 .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
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| /u-boot/arch/arm/mach-keystone/ |
| A D | ddr3_spd.c | 36 debug_ddr_cfg("mr1 0x%08X\n", ptr->mr1); in dump_phy_config()
351 spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 | in init_ddr3param()
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| A D | ddr3.c | 56 __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); in ddr3_init_ddrphy()
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| /u-boot/arch/mips/mach-jz47xx/jz4780/ |
| A D | sdram.c | 79 writel(ddr_config->mr1, ddr_phy_regs + DDRP_MR1); in ddr_phy_init()
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| /u-boot/arch/mips/mach-jz47xx/include/mach/ |
| A D | jz4780_dram.h | 439 u16 mr1; /* Mode Register 1 */ member
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| /u-boot/arch/arm/mach-omap2/omap5/ |
| A D | sdram.c | 441 .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
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| /u-boot/arch/arm/include/asm/ |
| A D | emif.h | 1243 s8 mr1; member
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| /u-boot/arch/arm/mach-omap2/ |
| A D | emif-common.c | 117 set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); in do_lpddr2_init()
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