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Searched refs:mrc (Results 1 – 25 of 75) sorted by relevance

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/u-boot/arch/x86/lib/
A Dmrccache.c198 cache->data_size = mrc->len; in mrccache_setup()
206 mrc->cache = cache; in mrccache_setup()
214 struct mrc_output *mrc = &gd->arch.mrc[i]; in mrccache_reserve() local
216 if (!mrc->len) in mrccache_reserve()
298 struct mrc_output *mrc; in mrccache_save_type() local
303 mrc = &gd->arch.mrc[type]; in mrccache_save_type()
304 if (!mrc->len) in mrccache_save_type()
307 mrc->len, type); in mrccache_save_type()
314 cache = mrc->cache; in mrccache_save_type()
345 struct mrc_output *mrc = &gd->arch.mrc[i]; in mrccache_spl_save() local
[all …]
/u-boot/arch/x86/lib/fsp1/
A Dfsp_dram.c21 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; in dram_init() local
23 mrc->buf = fsp_get_nvs_data(gd->arch.hob_list, &mrc->len); in dram_init()
/u-boot/arch/x86/lib/fsp2/
A Dfsp_dram.c51 gd->arch.mrc[MRC_TYPE_NORMAL].buf = in dram_init()
53 &gd->arch.mrc[MRC_TYPE_NORMAL].len); in dram_init()
54 gd->arch.mrc[MRC_TYPE_VAR].buf = in dram_init()
56 &gd->arch.mrc[MRC_TYPE_VAR].len); in dram_init()
58 gd->arch.mrc[MRC_TYPE_NORMAL].len, in dram_init()
59 gd->arch.mrc[MRC_TYPE_VAR].len); in dram_init()
/u-boot/arch/arm/cpu/armv7/
A Dstart.S83 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
106 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
197 mrc p15, 0, r0, c1, c0, 0
216 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
222 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
267 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
281 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
306 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
317 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
331 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
[all …]
A Dnonsec_virt.S32 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
61 mrc p15, 0, r5, c1, c0, 1
68 mrc p15, 0, r5, c1, c0, 1
74 mrc p15, 0, r5, c1, c1, 0 @ read SCR
93 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
118 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
180 mrc p15, 0, r0, c1, c1, 2
193 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
/u-boot/arch/arm/mach-rmobile/
A Dlowlevel_init_ca15.S15 mrc p15, 0, r4, c0, c0, 5 /* mpidr */
53 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
59 mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
73 mrc p15, 0, r0, c1, c0, 1
/u-boot/doc/device-tree-bindings/misc/
A Dintel,baytrail-fsp.txt34 - fsp,mrc-debug-msg
51 - fsp,mrc-init-tseg-size
52 - fsp,mrc-init-mmio-size
53 - fsp,mrc-init-spd-addr1
54 - fsp,mrc-init-spd-addr2
102 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
103 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
104 fsp,mrc-init-spd-addr1 = <0xa0>;
105 fsp,mrc-init-spd-addr2 = <0xa2>;
/u-boot/arch/x86/cpu/broadwell/
A Dsdram.c174 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; in dram_init() local
180 mrc->buf = (char *)pei_data->data_to_save; in dram_init()
181 mrc->len = pei_data->data_to_save_size; in dram_init()
/u-boot/arch/arm/mach-mediatek/mt7629/
A Dlowlevel_init.S32 mrc p15, 0, r1, c1, c1, 0 @ Get Secure Config
44 mrc p15, 0, r0, c1, c0, 1
49 mrc p15, 0, r0, c0, c0, 5
/u-boot/arch/arm/mach-uniphier/arm32/
A Dpsci_smp.S14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
26 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
A Dlowlevel_init.S23 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
42 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
53 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
74 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
/u-boot/arch/x86/cpu/quark/
A Ddram.c160 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; in dram_init() local
163 mrc->buf = cache; in dram_init()
164 mrc->len = sizeof(struct mrc_timings); in dram_init()
A DMakefile6 obj-y += mrc.o mrc_util.o hte.o smc.o
/u-boot/arch/arm/cpu/armv7/sunxi/
A Dfel_utils.S19 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
21 mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
/u-boot/arch/x86/dts/
A Dcherryhill.dts155 rw-mrc-cache {
156 label = "rw-mrc-cache";
168 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
169 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
170 fsp,mrc-init-spd-addr1 = <0xa0>;
171 fsp,mrc-init-spd-addr2 = <0xa2>;
A Dgalileo.dts8 #include <dt-bindings/mrc/quark.h>
45 mrc {
46 compatible = "intel,quark-mrc";
141 rw-mrc-cache {
142 label = "rw-mrc-cache";
A Dbayleybay.dts183 rw-mrc-cache {
184 label = "rw-mrc-cache";
242 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
243 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
244 fsp,mrc-init-spd-addr1 = <0xa0>;
245 fsp,mrc-init-spd-addr2 = <0xa2>;
A Dbaytrail_som-db5800-som-6867.dts207 rw-mrc-cache {
208 label = "rw-mrc-cache";
266 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
267 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
268 fsp,mrc-init-spd-addr1 = <0xa0>;
269 fsp,mrc-init-spd-addr2 = <0xa2>;
A Dchromebox_panther.dts55 rw-mrc-cache {
56 label = "rw-mrc-cache";
/u-boot/doc/board/google/
A Dchromebook_samus.rst11 * mrc.bin - Memory Reference Code, which sets up SDRAM
60 mrc.bin 0x79ffc0 (unknown) 222876
68 cbfstool samus.bin extract -n mrc.bin -f mrc.bin
98 :ffbe0000: rw-mrc-cache (Memory-reference-code cache)
A Dchromebook_link.rst11 * mrc.bin - Memory Reference Code, which sets up SDRAM
25 The 3rd one should be renamed to mrc.bin.
/u-boot/arch/arm/cpu/arm926ejs/
A Dstart.S85 mrc p15, 0, r15, c7, c10, 3
95 mrc p15, 0, r0, c1, c0, 0
/u-boot/board/xilinx/common/
A Dfru_ops.c240 struct fru_multirec_hdr mrc; in fru_parse_multirec() local
248 memcpy(&mrc.rec_type, (void *)addr, hdr_len); in fru_parse_multirec()
256 if (mrc.rec_type == FRU_MULTIREC_TYPE_OEM) { in fru_parse_multirec()
264 mac_len = mrc.len - FRU_MULTIREC_MAC_OFFSET; in fru_parse_multirec()
268 addr += mrc.len + hdr_len; in fru_parse_multirec()
269 } while (!(mrc.type & FRU_LAST_REC)); in fru_parse_multirec()
/u-boot/tools/binman/test/
A D050_intel_mrc.dts10 intel-mrc {
/u-boot/arch/arm/mach-k3/
A Dlowlevel_init.S11 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR

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