Home
last modified time | relevance | path

Searched refs:mult (Results 1 – 25 of 64) sorted by relevance

123

/u-boot/drivers/clk/
A Dclk-fixed-factor.c32 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
43 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor() argument
54 fix->mult = mult; in clk_hw_register_fixed_factor()
71 unsigned int mult, unsigned int div) in clk_register_fixed_factor() argument
75 clk = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult, in clk_register_fixed_factor()
A Dclk_fixed_factor.c20 unsigned int mult; member
37 return rate * ff->mult; in clk_fixed_factor_get_rate()
55 ff->mult = dev_read_u32_default(dev, "clock-mult", 1); in clk_fixed_factor_of_to_plat()
/u-boot/cmd/
A Dsleep.c28 uint mult = CONFIG_SYS_HZ / 10; in do_sleep() local
29 for (frpart++; *frpart != '\0' && mult > 0; frpart++) { in do_sleep()
34 mdelay += (*frpart - '0') * mult; in do_sleep()
35 mult /= 10; in do_sleep()
/u-boot/arch/arm/dts/
A Domap36xx-omap3430es2plus-clocks.dtsi35 clock-mult = <1>;
51 clock-mult = <1>;
75 clock-mult = <1>;
83 clock-mult = <1>;
91 clock-mult = <1>;
99 clock-mult = <1>;
107 clock-mult = <1>;
115 clock-mult = <1>;
123 clock-mult = <1>;
131 clock-mult = <1>;
[all …]
A Dam43xx-clocks.dtsi36 clock-mult = <1>;
44 clock-mult = <1>;
52 clock-mult = <1>;
60 clock-mult = <1>;
68 clock-mult = <1>;
76 clock-mult = <1>;
84 clock-mult = <1>;
92 clock-mult = <1>;
100 clock-mult = <1>;
318 clock-mult = <1>;
[all …]
A Dam33xx-clocks.dtsi20 clock-mult = <1>;
28 clock-mult = <1>;
36 clock-mult = <1>;
44 clock-mult = <1>;
52 clock-mult = <1>;
60 clock-mult = <1>;
68 clock-mult = <1>;
76 clock-mult = <1>;
84 clock-mult = <1>;
92 clock-mult = <1>;
[all …]
A Domap36xx-clocks.dtsi71 clock-mult = <1>;
75 clock-mult = <1>;
79 ti,clock-mult = <1>;
83 ti,clock-mult = <1>;
87 clock-mult = <1>;
A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi12 clock-mult = <1>;
20 clock-mult = <1>;
55 clock-mult = <1>;
63 clock-mult = <1>;
71 clock-mult = <1>;
79 clock-mult = <1>;
87 clock-mult = <1>;
A Dkeystone-clocks.dtsi28 clock-mult = <1>;
37 clock-mult = <1>;
66 clock-mult = <1>;
75 clock-mult = <1>;
84 clock-mult = <1>;
93 clock-mult = <1>;
102 clock-mult = <1>;
111 clock-mult = <1>;
120 clock-mult = <1>;
129 clock-mult = <1>;
[all …]
A Domap3xxx-clocks.dtsi43 clock-mult = <2>;
51 clock-mult = <2>;
59 clock-mult = <2>;
67 clock-mult = <1>;
75 clock-mult = <1>;
213 clock-mult = <2>;
230 clock-mult = <1>;
255 clock-mult = <2>;
272 clock-mult = <1>;
302 clock-mult = <1>;
[all …]
A Ddra7xx-clocks.dtsi108 clock-mult = <1>;
287 clock-mult = <1>;
313 clock-mult = <1>;
321 clock-mult = <1>;
359 clock-mult = <1>;
397 clock-mult = <1>;
446 clock-mult = <1>;
506 clock-mult = <1>;
514 clock-mult = <1>;
522 clock-mult = <1>;
[all …]
A Domap34xx-omap36xx-clocks.dtsi12 clock-mult = <1>;
77 clock-mult = <1>;
125 clock-mult = <1>;
149 clock-mult = <1>;
A Domap44xx-clocks.dtsi161 clock-mult = <1>;
233 clock-mult = <1>;
289 clock-mult = <1>;
407 clock-mult = <1>;
415 clock-mult = <1>;
441 clock-mult = <1>;
449 clock-mult = <1>;
466 clock-mult = <1>;
505 clock-mult = <1>;
705 clock-mult = <1>;
[all …]
A Dbcm63138.dtsi52 clock-mult = <1>;
61 clock-mult = <1>;
/u-boot/drivers/clk/microchip/
A Dmpfs_clk_msspll.c63 u32 mult, ref_div, postdiv; in mpfs_clk_msspll_recalc_rate() local
66 mult = readl(mult_addr) >> MSSPLL_FBDIV_SHIFT; in mpfs_clk_msspll_recalc_rate()
67 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
74 return temp * mult; in mpfs_clk_msspll_recalc_rate()
/u-boot/drivers/clk/renesas/
A Dclk-rcar-gen2.c78 u32 value, mult, div, rate = 0; in gen2_clk_get_rate() local
119 rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div; in gen2_clk_get_rate()
122 core->parent, core->mult, core->div, rate); in gen2_clk_get_rate()
147 mult = pll_config->pll0_mult; in gen2_clk_get_rate()
148 if (!mult) { in gen2_clk_get_rate()
150 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen2_clk_get_rate()
153 rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div; in gen2_clk_get_rate()
155 __func__, __LINE__, core->parent, mult, rate); in gen2_clk_get_rate()
A Drenesas-cpg-mssr.h63 unsigned int mult; member
87 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
91 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
93 DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
A Dclk-rcar-gen3.c165 u32 mul_reg, u32 mult, u32 div, in gen3_clk_get_rate64_pll_mul_reg() argument
173 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate64_pll_mul_reg()
177 rate = (gen3_clk_get_rate64(parent) * mult) / div; in gen3_clk_get_rate64_pll_mul_reg()
180 __func__, __LINE__, name, mult, div, rate); in gen3_clk_get_rate64_pll_mul_reg()
312 0, core->mult, core->div, in gen3_clk_get_rate64()
/u-boot/drivers/clk/mvebu/
A Darmada-37xx-tbg.c57 unsigned int mult[NUM_TBG]; member
128 unsigned int mult, div; in armada_37xx_tbg_clk_probe() local
130 mult = tbg_get_mult(reg, &tbg[i]); in armada_37xx_tbg_clk_probe()
133 priv->rates[i] = (xtal * mult) / div; in armada_37xx_tbg_clk_probe()
/u-boot/doc/device-tree-bindings/clock/
A Dfixed-factor-clock.txt11 - clock-mult: fixed multiplier.
23 clock-mult = <1>;
/u-boot/arch/arm/mach-keystone/
A Dclock.c70 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
282 unsigned long mult = 1, prediv = 1, output_div = 2; in pll_freq_get() local
292 mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >> in pll_freq_get()
294 (pllctl_reg_read(pll, mult) & in pll_freq_get()
300 ret = ret / prediv / output_div * mult; in pll_freq_get()
333 mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >> in pll_freq_get()
337 ret = ((ret / prediv) * mult) / output_div; in pll_freq_get()
/u-boot/include/
A Dsandbox-clk.h37 unsigned int mult, in sandbox_clk_fixed_factor() argument
41 CLK_SET_RATE_PARENT, mult, div); in sandbox_clk_fixed_factor()
/u-boot/arch/arm/mach-imx/imx8ulp/
A Dcgc.c399 u32 reg, infreq, mult; in decode_pll() local
415 mult = (reg >> 16) & 0x7F; in decode_pll()
419 return (u64)infreq * mult + (u64)infreq * num / denom; in decode_pll()
426 mult = (reg >> 16) & 0x7F; in decode_pll()
430 return (u64)infreq * mult + (u64)infreq * num / denom; in decode_pll()
437 mult = (reg >> 16) & 0x7F; in decode_pll()
441 return (u64)infreq * mult + (u64)infreq * num / denom; in decode_pll()
/u-boot/drivers/clk/ti/
A Dclk-am3-dpll.c48 int mult = INT_MAX, div = INT_MAX; in clk_ti_am3_dpll_round_rate() local
67 mult = m; in clk_ti_am3_dpll_round_rate()
78 priv->last_rounded_mult = mult; in clk_ti_am3_dpll_round_rate()
81 rate, priv->min_div, ret, mult, div); in clk_ti_am3_dpll_round_rate()
/u-boot/drivers/clk/mediatek/
A Dclk-mtk.h87 u32 mult; member
95 .mult = _mult, \

Completed in 26 milliseconds

123