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Searched refs:mxc_ccm (Results 1 – 25 of 28) sorted by relevance

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/u-boot/arch/arm/mach-imx/mx5/
A Dclock.c270 reg = readl(&mxc_ccm->cbcdr); in get_periph_clk()
273 reg = readl(&mxc_ccm->cbcmr); in get_periph_clk()
296 reg = readl(&mxc_ccm->cbcdr); in get_ipg_clk()
656 &mxc_ccm->ccsr); in config_pll_clk()
662 &mxc_ccm->ccsr); in config_pll_clk()
667 &mxc_ccm->ccsr); in config_pll_clk()
673 &mxc_ccm->ccsr); in config_pll_clk()
678 &mxc_ccm->ccsr); in config_pll_clk()
684 &mxc_ccm->ccsr); in config_pll_clk()
690 &mxc_ccm->ccsr); in config_pll_clk()
[all …]
/u-boot/board/engicam/imx6q/
A Dimx6q.c59 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
71 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
79 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
150 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
152 writel(reg, &mxc_ccm->CCGR3); in setup_display()
155 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
160 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
162 reg = readl(&mxc_ccm->cscmr2); in setup_display()
164 writel(reg, &mxc_ccm->cscmr2); in setup_display()
166 reg = readl(&mxc_ccm->chsccdr); in setup_display()
[all …]
/u-boot/board/engicam/imx6ul/
A Dimx6ul.c51 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
56 clrbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
68 clrbits_le32(&mxc_ccm->cscmr1, in setup_gpmi_nand()
71 clrsetbits_le32(&mxc_ccm->cscdr1, in setup_gpmi_nand()
78 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
86 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/u-boot/arch/arm/mach-imx/mx6/
A Dclock.c1485 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
1487 writel(reg, &mxc_ccm->ccdr); in select_ldb_di_clock_source()
1490 reg = readl(&mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1492 writel(reg, &mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1498 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1506 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1508 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1533 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1535 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1549 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
[all …]
A Dsoc.c310 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in set_ahb_rate() local
314 reg = readl(&mxc_ccm->cbcdr); in set_ahb_rate()
317 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); in set_ahb_rate()
322 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in clear_mmdc_ch_mask() local
324 reg = readl(&mxc_ccm->ccdr); in clear_mmdc_ch_mask()
331 writel(reg, &mxc_ccm->ccdr); in clear_mmdc_ch_mask()
670 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in imx_setup_hdmi() local
676 reg = readl(&mxc_ccm->CCGR2); in imx_setup_hdmi()
679 writel(reg, &mxc_ccm->CCGR2); in imx_setup_hdmi()
681 reg = readl(&mxc_ccm->chsccdr); in imx_setup_hdmi()
[all …]
/u-boot/board/ge/mx53ppd/
A Dmx53ppd_video.c30 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in lcd_enable() local
34 clrsetbits_le32(&mxc_ccm->cscmr2, in lcd_enable()
40 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3)); in lcd_enable()
43 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3)); in lcd_enable()
/u-boot/board/phytec/pcm058/
A Dpcm058.c40 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
43 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
46 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
55 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
58 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
66 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/u-boot/board/technexion/pico-imx6/
A Dpico-imx6.c238 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
252 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
254 writel(reg, &mxc_ccm->CCGR3); in setup_display()
257 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
262 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
264 reg = readl(&mxc_ccm->cscmr2); in setup_display()
266 writel(reg, &mxc_ccm->cscmr2); in setup_display()
268 reg = readl(&mxc_ccm->chsccdr); in setup_display()
273 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/u-boot/board/variscite/dart_6ul/
A Ddart_6ul.c59 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
64 clrbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
76 clrbits_le32(&mxc_ccm->cscmr1, in setup_gpmi_nand()
79 clrsetbits_le32(&mxc_ccm->cscdr1, in setup_gpmi_nand()
86 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
94 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/u-boot/board/ge/bx50v3/
A Dbx50v3.c204 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display_b850v3() local
210 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_b850v3()
215 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_b850v3()
221 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_b850v3()
245 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display_bx50v3() local
258 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_bx50v3()
261 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_bx50v3()
267 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_bx50v3()
/u-boot/board/freescale/mx6sabreauto/
A Dmx6sabreauto.c236 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
246 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
364 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
373 reg = readl(&mxc_ccm->CCGR3); in setup_display()
375 writel(reg, &mxc_ccm->CCGR3); in setup_display()
378 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
383 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
385 reg = readl(&mxc_ccm->cscmr2); in setup_display()
387 writel(reg, &mxc_ccm->cscmr2); in setup_display()
389 reg = readl(&mxc_ccm->chsccdr); in setup_display()
[all …]
/u-boot/board/kosagi/novena/
A Dvideo.c389 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display_clock() local
397 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_clock()
400 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_display_clock()
405 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_clock()
408 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_clock()
/u-boot/board/k+p/kp_imx6q_tpc/
A Dkp_imx6q_tpc.c113 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in board_init() local
119 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); in board_init()
/u-boot/board/freescale/mx6sabresd/
A Dmx6sabresd.c373 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
384 reg = readl(&mxc_ccm->CCGR3); in setup_display()
386 writel(reg, &mxc_ccm->CCGR3); in setup_display()
389 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
394 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
396 reg = readl(&mxc_ccm->cscmr2); in setup_display()
398 writel(reg, &mxc_ccm->cscmr2); in setup_display()
400 reg = readl(&mxc_ccm->chsccdr); in setup_display()
405 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/u-boot/board/embest/mx6boards/
A Dmx6boards.c311 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
319 setbits_le32(&mxc_ccm->CCGR3, in setup_display()
323 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_display()
327 setbits_le32(&mxc_ccm->cscmr2, in setup_display()
330 setbits_le32(&mxc_ccm->chsccdr, in setup_display()
/u-boot/board/dhelectronics/dh_imx6/
A Ddh_imx6.c119 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in board_init() local
125 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); in board_init()
/u-boot/board/toradex/colibri_imx6/
A Dcolibri_imx6.c503 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
510 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
512 writel(reg, &mxc_ccm->CCGR3); in setup_display()
515 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
520 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
522 reg = readl(&mxc_ccm->cscmr2); in setup_display()
524 writel(reg, &mxc_ccm->cscmr2); in setup_display()
526 reg = readl(&mxc_ccm->chsccdr); in setup_display()
529 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/u-boot/board/toradex/apalis_imx6/
A Dapalis_imx6.c583 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
590 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
592 writel(reg, &mxc_ccm->CCGR3); in setup_display()
595 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
600 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
602 reg = readl(&mxc_ccm->cscmr2); in setup_display()
604 writel(reg, &mxc_ccm->cscmr2); in setup_display()
606 reg = readl(&mxc_ccm->chsccdr); in setup_display()
609 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/u-boot/board/boundary/nitrogen6x/
A Dnitrogen6x.c706 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
713 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
715 writel(reg, &mxc_ccm->CCGR3); in setup_display()
718 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
723 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
725 reg = readl(&mxc_ccm->cscmr2); in setup_display()
727 writel(reg, &mxc_ccm->cscmr2); in setup_display()
729 reg = readl(&mxc_ccm->chsccdr); in setup_display()
732 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/u-boot/board/gateworks/gw_ventana/
A Dgw_ventana.c300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
307 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
309 writel(reg, &mxc_ccm->CCGR3); in setup_display()
312 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
317 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
319 reg = readl(&mxc_ccm->cscmr2); in setup_display()
321 writel(reg, &mxc_ccm->cscmr2); in setup_display()
323 reg = readl(&mxc_ccm->chsccdr); in setup_display()
326 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/u-boot/board/freescale/mx51evk/
A Dmx51evk.c85 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; in power_init() local
127 writel(0x0, &mxc_ccm->cacrr); in power_init()
/u-boot/board/ge/b1x5v2/
A Db1x5v2.c268 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
282 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display()
286 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display()
292 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display()
/u-boot/drivers/video/imx/
A Dipu_common.c28 extern struct mxc_ccm_reg *mxc_ccm;
171 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_enable()
173 __raw_writel(reg, &mxc_ccm->ccdr); in clk_ipu_enable()
176 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_enable()
178 __raw_writel(reg, &mxc_ccm->clpcr); in clk_ipu_enable()
196 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_disable()
198 __raw_writel(reg, &mxc_ccm->ccdr); in clk_ipu_disable()
201 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_disable()
203 __raw_writel(reg, &mxc_ccm->clpcr); in clk_ipu_disable()
/u-boot/board/compulab/cm_fx6/
A Dspl.c317 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in board_init_f() local
324 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in board_init_f()
/u-boot/board/wandboard/
A Dwandboard.c334 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
340 reg = readl(&mxc_ccm->chsccdr); in setup_display()
343 writel(reg, &mxc_ccm->chsccdr); in setup_display()

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