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Searched refs:operation (Results 1 – 25 of 115) sorted by relevance

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/u-boot/arch/arm/mach-uniphier/arm32/
A Dcache-uniphier.c95 u32 operation) in uniphier_cache_maint_common() argument
102 writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM); in uniphier_cache_maint_common()
105 if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) { in uniphier_cache_maint_common()
111 if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation))) in uniphier_cache_maint_common()
121 static void uniphier_cache_maint_all(u32 operation) in uniphier_cache_maint_all() argument
123 uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation); in uniphier_cache_maint_all()
129 u32 operation) in uniphier_cache_maint_range() argument
143 uniphier_cache_maint_all(operation); in uniphier_cache_maint_range()
157 UNIPHIER_SSCOQM_S_RANGE | operation); in uniphier_cache_maint_range()
/u-boot/include/xen/interface/io/
A Dblkif.h631 u8 operation; /* BLKIF_OP_??? */ member
644 u8 operation; /* BLKIF_OP_DISCARD */ member
654 u8 operation; /* BLKIF_OP_INDIRECT */ member
668 u8 operation; /* copied from request */ member
/u-boot/lib/efi_loader/
A Defi_gop.c110 u32 operation, efi_uintn_t sx, in gop_blt_int() argument
134 switch (operation) { in gop_blt_int()
152 switch (operation) { in gop_blt_int()
167 switch (operation) { in gop_blt_int()
182 switch (operation) { in gop_blt_int()
202 switch (operation) { in gop_blt_int()
224 switch (operation) { in gop_blt_int()
405 u32 operation, efi_uintn_t sx, in gop_blt() argument
419 switch (operation) { in gop_blt()
427 ret = gop_blt_buf_to_vid32(this, buffer, operation, sx, in gop_blt()
[all …]
/u-boot/doc/device-tree-bindings/misc/
A Dcros-ec.txt4 The device tree node which describes the operation of the CROS_EC interface
12 operation
14 operation
/u-boot/drivers/usb/dwc3/
A DKconfig31 This wrapper supports Host and Peripheral operation modes.
38 This wrapper supports Host and Peripheral operation modes.
46 This wrapper supports Host and Peripheral operation modes.
54 This wrapper supports Host and Peripheral operation modes.
73 Host and Peripheral operation modes are supported. OTG is not
/u-boot/doc/usage/cmd/
A Dmmc.rst119 x1 (sdr) or x4(ddr) buswidth in boot operation mode (default)
121 x4 (sdr/ddr) buswidth in boot operation mode
123 x8 (sdr/ddr) buswidth in boot operation mode
129 …set buswidth to x1, Single data reate and backward compatible timing after boot operation (default)
131 …in BOOT_BUS_WIDTH and BOOT_MODE value after boot operation. This is relevant to Push-pull mode ope…
135 Use single data rate + backward compatible timing in boot operation (default)
137 Use single data rate + High Speed timing in boot operation mode
139 Use dual data rate in boot operation
/u-boot/doc/
A DREADME.fuse7 (i.e. blown, set to 1) only once. The programming operation is irreversible. A
34 fuse words. This operation does not update the shadow cache.
41 Program fuse words. This operation directly affects the fusebox and is
49 hardware programming operation on these fuse bits).
55 The fusebox is unaffected, so following this operation, the shadow cache
/u-boot/tools/binman/test/
A D226_fit_split_elf.dts24 fit,operation = "split-elf";
42 fit,operation = "split-elf";
A D224_fit_bad_oper.dts17 fit,operation = "unknown";
A D264_tee_os_opt_fit.dts17 fit,operation = "split-elf";
A D265_tee_os_opt_fit_bad.dts17 fit,operation = "split-elf";
A D223_fit_fdt_oper.dts36 fit,operation = "gen-fdt-nodes";
/u-boot/drivers/mtd/nand/raw/
A Dmxc_nand_spl.c124 writenfc(NFC_CMD, &nfc->operation); in nfc_nand_command()
131 writenfc(NFC_ADDR, &nfc->operation); in nfc_nand_address()
172 writenfc(NFC_OUTPUT, &nfc->operation); in nfc_nand_data_output()
181 writenfc(NFC_OUTPUT, &nfc->operation); in nfc_nand_data_output()
A Dmxc_nand.h194 #define operation config2 macro
198 #define operation launch macro
/u-boot/arch/arm/dts/
A Dimx6q-cm-fx6.dts171 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
173 * 1.2GHz operation point here.
193 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
195 * 1.2GHz operation point here.
215 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
217 * 1.2GHz operation point here.
237 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
239 * 1.2GHz operation point here.
A Drockchip-u-boot.dtsi64 fit,operation = "split-elf";
83 fit,operation = "split-elf";
/u-boot/board/freescale/ls1028a/
A DREADME33 - Up to 1.3 GHz operation
112 - Up to 1.3 GHz operation
129 - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
131 - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
133 - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
135 - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
/u-boot/arch/mips/mach-mtmips/mt7621/tpl/
A Dstart.S29 li t9, 15 # UHI exception operation
31 sdbbp 1 # Invoke UHI operation
/u-boot/board/socionext/developerbox/
A DKconfig17 the dcache is updated automatically when DMA operation is executed.
/u-boot/drivers/mtd/nvmxip/
A DKconfig13 This support provides the read operation.
/u-boot/doc/device-tree-bindings/i2c/
A Dtegra20-i2c.txt9 - the pll_p_out3 clock, which can be used for fast operation. This
/u-boot/doc/device-tree-bindings/ata/
A Dintel-sata.txt4 The device tree node which describes the operation of the Intel Pantherpoint
/u-boot/arch/mips/cpu/
A Dstart.S36 li t9, 15 # UHI exception operation
38 sdbbp 1 # Invoke UHI operation
/u-boot/board/ti/dra7xx/
A DREADME12 Alternative Boot operation mode or Boot Sequence Option 1/2. In this
/u-boot/doc/device-tree-bindings/reset/
A Dsyscon-reset.txt8 To assert a reset on some device, the equivalent of the following operation is

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