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Searched refs:pcie (Results 1 – 25 of 324) sorted by relevance

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/u-boot/drivers/pci/
A Dpcie_layerscape_gen4.c192 if (!pcie->enabled) in ls_pcie_g4_addr_valid()
459 pcie->bus = dev; in ls_pcie_g4_probe()
468 pcie->idx = (pcie->ccsr_res.start - PCIE_SYS_BASE_ADDR) / in ls_pcie_g4_probe()
473 pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); in ls_pcie_g4_probe()
474 if (!pcie->enabled) { in ls_pcie_g4_probe()
480 pcie->ccsr = map_physmem(pcie->ccsr_res.start, in ls_pcie_g4_probe()
498 pcie->cfg = map_physmem(pcie->cfg_res.start, in ls_pcie_g4_probe()
509 pcie->lut = map_physmem(pcie->lut_res.start, in ls_pcie_g4_probe()
520 pcie->pf_ctrl = map_physmem(pcie->pf_ctrl_res.start, in ls_pcie_g4_probe()
527 dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg, in ls_pcie_g4_probe()
[all …]
A Dpcie_layerscape.c26 return in_le32(pcie->dbi + offset); in dbi_readl()
31 out_le32(pcie->dbi + offset, value); in dbi_writel()
36 if (pcie->big_endian) in ctrl_readl()
37 return in_be32(pcie->ctrl + offset); in ctrl_readl()
45 if (pcie->big_endian) in ctrl_writel()
56 val = dbi_readl(pcie, reg); in ls_pcie_dbi_ro_wr_en()
58 dbi_writel(pcie, val, reg); in ls_pcie_dbi_ro_wr_en()
66 val = dbi_readl(pcie, reg); in ls_pcie_dbi_ro_wr_dis()
68 dbi_writel(pcie, val, reg); in ls_pcie_dbi_ro_wr_dis()
78 state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx)); in ls_pcie_ltssm()
[all …]
A Dpci_mvebu.c264 mvebu_pcie_set_local_bus_nr(pcie, pcie->sec_busno); in mvebu_pcie_write_config()
358 writel(pcie->intregs, pcie->base + MVPCIE_BAR_LO_OFF(0)); in mvebu_pcie_setup_wins()
530 pcie->mem.start, pcie->mem.start, in mvebu_pcie_probe()
538 pcie->io.start, pcie->io.start, in mvebu_pcie_probe()
637 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane); in mvebu_pcie_port_parse_dt()
652 &pcie->mem_target, &pcie->mem_attr); in mvebu_pcie_port_parse_dt()
660 &pcie->io_target, &pcie->io_attr); in mvebu_pcie_port_parse_dt()
675 pcie->intregs = (u32)pcie->base - fdt32_to_cpu(addr[2]); in mvebu_pcie_port_parse_dt()
746 pcie = calloc(1, sizeof(*pcie)); in mvebu_pcie_bind()
747 if (!pcie) in mvebu_pcie_bind()
[all …]
A Dpci-aardvark.c172 writel(val, pcie->base + reg); in advk_writel()
177 return readl(pcie->base + reg); in advk_readl()
402 if (pcie->cfgcrssve) in pcie_advk_read_config()
431 dev_err(pcie->dev, in pcie_advk_read_config()
444 if (busno == pcie->sec_busno) in pcie_advk_read_config()
592 dev_err(pcie->dev, in pcie_advk_write_config()
600 if (busno == pcie->sec_busno) in pcie_advk_write_config()
725 dev_dbg(pcie->dev, in pcie_advk_set_ob_region()
740 dev_err(pcie->dev, in pcie_advk_set_ob_region()
896 pcie_advk_wait_for_link(pcie); in pcie_advk_setup_hw()
[all …]
A Dpcie_layerscape_rc.c32 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_cfg0_set_busdev() local
41 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_cfg1_set_busdev() local
52 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_setup_atu() local
132 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_addr_valid() local
156 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_conf_address() local
200 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_clear_multifunction() local
208 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_fix_class() local
216 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_drop_msg_tlp() local
267 pcie_rc->pcie = pcie; in ls_pcie_probe()
321 pcie->ctrl = pcie->lut; in ls_pcie_probe()
[all …]
A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
113 return readl(pcie->cra_base + reg); in cra_readl()
126 if (!IS_ROOT_PORT(pcie, bdf) && !intel_fpga_pcie_link_up(pcie)) in intel_fpga_pcie_addr_valid()
193 tlp_write_tx(pcie, headers[1], 0); in tlp_write_packet()
195 tlp_write_tx(pcie, headers[2], 0); in tlp_write_packet()
289 if (IS_ROOT_PORT(pcie, bdf)) in _pcie_intel_fpga_read_config()
319 if (IS_ROOT_PORT(pcie, bdf)) in _pcie_intel_fpga_write_config()
[all …]
A Dpcie_fsl.c30 if (!pcie->enabled) in fsl_pcie_addr_valid()
36 if (PCI_BUS(bdf) > dev_seq(bus) && (!fsl_pcie_link_up(pcie) || pcie->mode)) in fsl_pcie_addr_valid()
576 pcie->bus = dev; in fsl_pcie_probe()
580 pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx); in fsl_pcie_probe()
581 if (!pcie->enabled) { in fsl_pcie_probe()
588 pcie->mode = fsl_pcie_is_agent(pcie); in fsl_pcie_probe()
594 if (pcie->mode) { in fsl_pcie_probe()
596 fsl_pcie_init_ep(pcie); in fsl_pcie_probe()
599 fsl_pcie_init_rc(pcie); in fsl_pcie_probe()
620 if (!pcie->regs) { in fsl_pcie_of_to_plat()
[all …]
A Dpcie_layerscape_gen4_fixup.c67 pcie->ccsr_res.start); in fdt_pcie_set_msi_map_entry_ls_gen4()
111 pcie->ccsr_res.start); in fdt_pcie_set_iommu_map_entry_ls_gen4()
143 struct ls_pcie_g4 *pcie; in fdt_fixup_pcie_ls_gen4() local
152 pcie = dev_get_priv(bus); in fdt_fixup_pcie_ls_gen4()
154 streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx); in fdt_fixup_pcie_ls_gen4()
159 pcie->stream_id_cur++; in fdt_fixup_pcie_ls_gen4()
195 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL) in ft_pcie_ep_layerscape_gen4_fix()
216 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE) in ft_pcie_rc_layerscape_gen4_fix()
227 pcie->stream_id_cur = 0; in ft_pcie_layerscape_gen4_setup()
228 pcie->next_lut_index = 0; in ft_pcie_layerscape_gen4_setup()
[all …]
A Dpcie_iproc.c464 if (!pcie->link_is_active) in iproc_pcie_map_ep_cfg_reg()
660 switch (pcie->type) { in iproc_pcie_rev_init()
670 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
686 if (!pcie->reg_offsets) in iproc_pcie_rev_init()
690 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? in iproc_pcie_rev_init()
1041 dev_dbg(pcie->dev, in iproc_pcie_map_dma_ranges()
1177 if (!pcie->base) in iproc_pcie_probe()
1183 pcie->dev = dev; in iproc_pcie_probe()
1205 iproc_pcie_reset(pcie); in iproc_pcie_probe()
1207 if (pcie->need_ob_cfg) { in iproc_pcie_probe()
[all …]
A Dpci_tegra.c197 struct tegra_pcie *pcie; member
301 *address = pcie->cs.start + in tegra_pcie_conf_address()
513 if (pcie->phy) { in tegra_pcie_parse_dt()
552 port->pcie = pcie; in tegra_pcie_parse_dt()
556 &pcie->xbar); in tegra_pcie_parse_dt()
731 if (pcie->phy) {
761 if (pcie->phy)
807 axi = pcie->cs.start;
918 struct tegra_pcie *pcie = port->pcie; local
924 value = afi_readl(pcie, ctrl);
[all …]
A Dpcie_dw_mvebu.c271 if (pcie->region_count > 1) in pcie_dw_mvebu_read_config()
274 pcie->io.bus_start, pcie->io.size); in pcie_dw_mvebu_read_config()
317 if (pcie->region_count > 1) in pcie_dw_mvebu_write_config()
320 pcie->io.bus_start, pcie->io.size); in pcie_dw_mvebu_write_config()
532 pcie->mem.phys_start = hose->regions[pcie->region_count - 1].phys_start; in pcie_dw_mvebu_probe()
534 pcie->mem.bus_start = hose->regions[pcie->region_count - 1].bus_start; in pcie_dw_mvebu_probe()
536 pcie->mem.size = hose->regions[pcie->region_count - 1].size; in pcie_dw_mvebu_probe()
540 pcie->mem.bus_start, pcie->mem.size); in pcie_dw_mvebu_probe()
568 if (!pcie->ctrl_base) in pcie_dw_mvebu_of_to_plat()
573 &pcie->cfg_size); in pcie_dw_mvebu_of_to_plat()
[all …]
A Dpcie_layerscape_ep.c23 struct ls_pcie *pcie = pcie_ep->pcie; in ls_pcie_ep_enable_cfg() local
34 struct ls_pcie *pcie = pcie_ep->pcie; in ls_ep_set_bar() local
71 struct ls_pcie *pcie = pcie_ep->pcie; in ls_pcie_ep_setup_atu() local
187 struct ls_pcie *pcie = pcie_ep->pcie; in ls_pcie_setup_ep() local
247 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in ls_pcie_ep_probe()
248 if (!pcie) in ls_pcie_ep_probe()
251 pcie_ep->pcie = pcie; in ls_pcie_ep_probe()
254 if (!pcie->dbi) in ls_pcie_ep_probe()
258 if (!pcie->ctrl) in ls_pcie_ep_probe()
269 pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) / in ls_pcie_ep_probe()
[all …]
A Dpcie_ecam_synquacer.c237 addr = pcie->cfg_base; in pci_synquacer_ecam_conf_address()
349 if (!pcie->dbi_base) { in pci_synquacer_ecam_of_to_plat()
356 if (!pcie->exs_base) { in pci_synquacer_ecam_of_to_plat()
362 pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE); in pci_synquacer_ecam_of_to_plat()
363 if (!pcie->cfg_base) { in pci_synquacer_ecam_of_to_plat()
367 debug("mappings DBI: %p EXS: %p CFG: %p\n", pcie->dbi_base, pcie->exs_base, pcie->cfg_base); in pci_synquacer_ecam_of_to_plat()
503 pcie->mem.size, in pci_synquacer_post_init()
520 (u64)pcie->io.phys_start - (u64)pcie->cfg_base - SIZE_64KB, in pci_synquacer_post_init()
527 pcie->io.bus_start, in pci_synquacer_post_init()
528 pcie->io.size, in pci_synquacer_post_init()
[all …]
A Dpcie_layerscape_gen4.h200 if (pcie->big_endian) in lut_writel()
201 out_be32(pcie->lut + offset, value); in lut_writel()
203 out_le32(pcie->lut + offset, value); in lut_writel()
208 if (pcie->big_endian) in lut_readl()
209 return in_be32(pcie->lut + offset); in lut_readl()
211 return in_le32(pcie->lut + offset); in lut_readl()
218 val = in_le32(pcie->ccsr + PAB_CTRL); in ccsr_set_page()
228 ccsr_set_page(pcie, 0); in ccsr_readl()
239 ccsr_set_page(pcie, 0); in ccsr_writel()
249 if (pcie->big_endian) in pf_ctrl_readl()
[all …]
A Dpcie_ecam_generic.c47 struct generic_ecam_pcie *pcie = dev_get_priv(bus); in pci_generic_ecam_conf_address() local
50 addr = pcie->cfg_base; in pci_generic_ecam_conf_address()
53 addr += ((PCI_BUS(bdf) - pcie->first_busno) << 16) | in pci_generic_ecam_conf_address()
67 struct generic_ecam_pcie *pcie = dev_get_priv(bus); in pci_generic_ecam_addr_valid() local
68 int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); in pci_generic_ecam_addr_valid()
70 return (PCI_BUS(bdf) >= pcie->first_busno && in pci_generic_ecam_addr_valid()
71 PCI_BUS(bdf) < pcie->first_busno + num_buses); in pci_generic_ecam_addr_valid()
134 struct generic_ecam_pcie *pcie = dev_get_priv(dev); in pci_generic_ecam_of_to_plat() local
146 pcie->size = fdt_resource_size(&reg_res); in pci_generic_ecam_of_to_plat()
147 pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE); in pci_generic_ecam_of_to_plat()
[all …]
A Dpcie_apple.c152 struct apple_pcie_priv *pcie; member
178 addr = pcie->cfg_base; in apple_pcie_config_address()
216 if (pcie->hw->phy_lane_ctl) in apple_pcie_setup_refclk()
235 if (pcie->hw->phy_lane_ctl) in apple_pcie_setup_refclk()
240 if (pcie->hw->port_refclk) in apple_pcie_setup_refclk()
269 port->pcie = pcie; in apple_pcie_setup_port()
325 if (pcie->hw->port_refclk) in apple_pcie_setup_port()
343 pcie->dev = dev; in apple_pcie_probe()
347 pcie->cfg_base = map_sysmem(addr, 0); in apple_pcie_probe()
352 pcie->base = map_sysmem(addr, 0); in apple_pcie_probe()
[all …]
A Dpcie_fsl_fixup.c17 static void ft_fsl_pcie_setup(void *blob, struct fsl_pcie *pcie) in ft_fsl_pcie_setup() argument
19 struct pci_controller *hose = dev_get_uclass_priv(pcie->bus); in ft_fsl_pcie_setup()
23 regs_addr = dev_read_addr(pcie->bus); in ft_fsl_pcie_setup()
31 if (!hose || !pcie->enabled) in ft_fsl_pcie_setup()
40 struct fsl_pcie *pcie; in pci_of_setup() local
42 list_for_each_entry(pcie, &fsl_pcie_list, list) in pci_of_setup()
43 ft_fsl_pcie_setup(blob, pcie); in pci_of_setup()
A Dpci_octeontx.c109 *valuep = readl_size(pcie->cfg.start + address, size); in octeontx_ecam_read_config()
127 writel_size(pcie->cfg.start + address, size, value); in octeontx_ecam_write_config()
143 u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; in octeontx_pem_read_config()
173 u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; in octeontx_pem_write_config()
213 *valuep = readl_size(pcie->cfg.start + address, size); in octeontx2_pem_read_config()
235 writel_size(pcie->cfg.start + address, size, value); in octeontx2_pem_write_config()
251 switch (pcie->type) { in pci_octeontx_read_config()
276 switch (pcie->type) { in pci_octeontx_write_config()
304 pcie->type = dev_get_driver_data(dev); in pci_octeontx_probe()
306 err = dev_read_resource(dev, 0, &pcie->cfg); in pci_octeontx_probe()
[all …]
A Dpcie_brcmstb.c222 *paddress = pcie->base + offset; in brcm_pcie_config_address()
388 void __iomem *base = pcie->base; in brcm_pcie_set_outbound_win()
429 void __iomem *base = pcie->base; in brcm_pcie_probe()
501 if (pcie->gen) in brcm_pcie_probe()
502 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_probe()
514 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_probe()
519 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_probe()
546 if (pcie->ssc) { in brcm_pcie_probe()
602 if (!pcie->base) in brcm_pcie_of_to_plat()
609 pcie->gen = 0; in brcm_pcie_of_to_plat()
[all …]
A Dpcie_dw_common.c121 int bus = PCI_BUS(d) - pcie->first_busno; in set_cfg_address()
128 va_address = (uintptr_t)pcie->dbi_base; in set_cfg_address()
151 atu_type, (u64)pcie->cfg_base, in set_cfg_address()
152 d << 8, pcie->cfg_size); in set_cfg_address()
156 va_address = (uintptr_t)pcie->cfg_base; in set_cfg_address()
203 struct pcie_dw *pcie = dev_get_priv(bus); in pcie_dw_read_config() local
224 PCIE_ATU_TYPE_IO, pcie->io.phys_start, in pcie_dw_read_config()
225 pcie->io.bus_start, pcie->io.size); in pcie_dw_read_config()
247 struct pcie_dw *pcie = dev_get_priv(bus); in pcie_dw_write_config() local
267 PCIE_ATU_TYPE_IO, pcie->io.phys_start, in pcie_dw_write_config()
[all …]
/u-boot/drivers/pci_endpoint/
A Dpcie-cadence.h239 writeb(value, pcie->reg_base + reg); in cdns_pcie_writeb()
244 writew(value, pcie->reg_base + reg); in cdns_pcie_writew()
249 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
254 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
258 static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, in cdns_pcie_rp_writeb() argument
261 writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writeb()
264 static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, in cdns_pcie_rp_writew() argument
267 writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writew()
270 static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie, in cdns_pcie_rp_writel() argument
273 writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writel()
[all …]
A Dpcie-cadence-ep.c21 struct cdns_pcie *pcie = dev_get_priv(dev); in cdns_write_header() local
25 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, in cdns_write_header()
27 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, in cdns_write_header()
30 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, in cdns_write_header()
32 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, in cdns_write_header()
34 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, in cdns_write_header()
46 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); in cdns_write_header()
54 struct cdns_pcie *pcie = dev_get_priv(dev); in cdns_set_bar() local
108 cfg = cdns_pcie_readl(pcie, reg); in cdns_set_bar()
113 cdns_pcie_writel(pcie, reg, cfg); in cdns_set_bar()
[all …]
/u-boot/arch/arm/dts/
A Dtegra210-p2371-2180.dts26 pcie@1003000 {
50 nvidia,lanes = "pcie-5", "pcie-6";
55 pcie-x1 {
56 nvidia,lanes = "pcie-0";
57 nvidia,function = "pcie-x1";
61 pcie-x4 {
62 nvidia,lanes = "pcie-1", "pcie-2",
63 "pcie-3", "pcie-4";
64 nvidia,function = "pcie-x4";
A Dtegra210-p3450-0000.dts18 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
33 pcie@1003000 {
66 nvidia,lanes = "pcie-5", "pcie-6";
71 pcie-x1 {
72 nvidia,lanes = "pcie-0";
73 nvidia,function = "pcie-x1";
77 pcie-x4 {
78 nvidia,lanes = "pcie-1", "pcie-2",
79 "pcie-3", "pcie-4";
80 nvidia,function = "pcie-x4";
/u-boot/doc/device-tree-bindings/pci/
A Darmada8k-pcie.txt7 - compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
8 - reg: base addresses and lengths of the pcie control and global control registers.
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
15 "Documentation/devicetree/bindings/pci/designware-pcie.txt"
19 - phys : phandle to phy node associated with pcie controller.
20 - phy-names : must be "pcie-phy"
25 cpm_pcie0: pcie@f2600000 {
26 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";

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