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Searched refs:phase (Results 1 – 25 of 139) sorted by relevance

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/u-boot/arch/arm/mach-stm32mp/cmd_stm32prog/
A Dstm32prog_usb.c20 if (phase == data->phase) { in stm32prog_set_phase()
29 if (part->id == phase) { in stm32prog_set_phase()
31 data->phase = phase; in stm32prog_set_phase()
43 u8 phase; in stm32prog_cmd_write() local
57 phase = pt[0]; in stm32prog_cmd_write()
59 if (phase == PHASE_RESET) { in stm32prog_cmd_write()
79 int phase; in stm32prog_cmd_read() local
91 phase = stm32prog_data->phase; in stm32prog_cmd_read()
92 if (phase == PHASE_FLASHLAYOUT) in stm32prog_cmd_read()
97 *pt_buf++ = (u8)(phase & 0xFF); in stm32prog_cmd_read()
[all …]
A Dstm32prog_serial.c123 if (phase == PHASE_FLASHLAYOUT || phase > PHASE_LAST_USER) { in stm32prog_read()
139 if (part->id == phase) in stm32prog_read()
165 data->read_phase = phase; in stm32prog_read()
172 ret, phase, offset); in stm32prog_read()
318 data->phase = address; in stm32prog_start()
329 switch (data->phase) { in stm32prog_start()
458 int phase = data->phase; in get_phase_command() local
460 if (phase == PHASE_RESET || phase == PHASE_DO_RESET) { in get_phase_command()
479 if (phase == PHASE_RESET) in get_phase_command()
800 int phase = data->phase; in stm32prog_serial_loop() local
[all …]
A Dstm32prog.c1341 int phase, i, alt_id; in dfu_init_entities() local
1379 for (phase = 1; in dfu_init_entities()
1382 phase++) { in dfu_init_entities()
1713 data->phase = PHASE_END; in stm32prog_end_phase()
1771 int phase, i; in stm32prog_next_phase() local
1775 phase = data->phase; in stm32prog_next_phase()
1776 switch (phase) { in stm32prog_next_phase()
1786 data->phase = PHASE_END; in stm32prog_next_phase()
1789 phase++; in stm32prog_next_phase()
1794 if (part->id == phase) { in stm32prog_next_phase()
[all …]
A Dstm32prog.h158 unsigned int phase; member
210 if (data->phase != PHASE_RESET) { \
212 data->phase = PHASE_RESET; \
/u-boot/drivers/ddr/marvell/axp/
A Dddr3_read_leveling.c339 u32 phase) in overrun() argument
413 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
519 if ((!ratio_2to1) && ((phase == 0) || (phase == 4))) in ddr3_read_leveling_single_cs_rl_mode()
561 phase++; in ddr3_read_leveling_single_cs_rl_mode()
573 phase++; in ddr3_read_leveling_single_cs_rl_mode()
590 phase++; in ddr3_read_leveling_single_cs_rl_mode()
765 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
879 phase; in ddr3_read_leveling_single_cs_window_mode()
989 phase++; in ddr3_read_leveling_single_cs_window_mode()
1124 phase = 4; in ddr3_read_leveling_single_cs_window_mode()
[all …]
A Dddr3_write_leveling.c119 phase = in ddr3_write_leveling_hw()
345 phase = in ddr3_wl_supplement()
353 [P] = phase; in ddr3_wl_supplement()
366 phase = in ddr3_wl_supplement()
375 if ((phase == 0) in ddr3_wl_supplement()
382 phase = 0x0; in ddr3_wl_supplement()
386 [P] = phase; in ddr3_wl_supplement()
439 phase = in ddr3_wl_supplement()
542 phase = in ddr3_write_leveling_hw_reg_dimm()
1223 for (phase = 0; phase < phaseMax; phase++) { in ddr3_write_leveling_single_cs()
[all …]
/u-boot/drivers/video/tidss/
A Dtidss_regs.h125 #define DSS_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
127 #define DSS_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
130 #define DSS_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
132 #define DSS_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
135 #define DSS_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
137 #define DSS_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
140 #define DSS_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
142 #define DSS_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
/u-boot/doc/device-tree-bindings/
A Dbootph.yaml8 title: Boot-phase-specific device nodes
18 of a boot phase, so cannot fit into every phase of the boot process. Even
25 Without any tags, nodes are included only in the final phase, where all
27 and are ignored before the final phase is reached.
29 The build process produces a separate executable for each phase. It can
34 Note that phase builds may drop the tags, since they have served their
35 purpose by that point. So when looking at phase-specific device tree files
51 The available tags are described as properties below, in order of phase
60 Enable this node when SRAM is not available. This phase must set up
73 Enable this node in the phase that sets up SDRAM.
[all …]
/u-boot/lib/efi_selftest/
A Defi_selftest_reset.c46 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
54 .phase = EFI_SETUP_BEFORE_BOOTTIME_EXIT,
A Defi_selftest.c162 if (test->phase == EFI_SETUP_BEFORE_BOOTTIME_EXIT || in need_reset()
163 test->phase == EFI_SETTING_VIRTUAL_ADDRESS_MAP) in need_reset()
212 void efi_st_do_tests(const u16 *testname, unsigned int phase, in efi_st_do_tests() argument
224 if (test->phase != phase) in efi_st_do_tests()
A Defi_selftest_unaligned.c63 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
/u-boot/drivers/usb/emul/
A Dsandbox_flash.c220 dev->name, pipe, ep, len, info->phase); in sandbox_flash_bulk()
223 switch (info->phase) { in sandbox_flash_bulk()
256 info->phase = SCSIPH_STATUS; in sandbox_flash_bulk()
263 info->phase = SCSIPH_STATUS; in sandbox_flash_bulk()
271 switch (info->phase) { in sandbox_flash_bulk()
286 info->phase = SCSIPH_STATUS; in sandbox_flash_bulk()
293 info->phase = SCSIPH_STATUS; in sandbox_flash_bulk()
301 info->phase = SCSIPH_START; in sandbox_flash_bulk()
/u-boot/arch/x86/include/asm/fsp/
A Dfsp_support.h38 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
155 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
A Dfsp_api.h29 enum fsp_phase phase; member
/u-boot/drivers/core/
A Ddevres.c47 enum devres_phase phase; member
111 dr->phase = DEVRES_PHASE_PROBE; in devres_add()
113 dr->phase = DEVRES_PHASE_OFDATA; in devres_add()
115 dr->phase = DEVRES_PHASE_BIND; in devres_add()
201 if (probe_and_ofdata_only && dr->phase == DEVRES_PHASE_BIND) in release_nodes()
233 devres_phase_name[dr->phase]); in dump_resources()
/u-boot/arch/x86/lib/fsp2/
A Dfsp_support.c111 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) in fsp_notify() argument
128 params.phase = phase; in fsp_notify()
/u-boot/drivers/net/octeon/
A Docteon_mdio.c168 smi_clk.s.phase = sclock / (p->speed * 2); in octeon_mdio_probe()
188 if (sample > (2 * smi_clk.s.phase - 3)) { in octeon_mdio_probe()
191 sample = 2 * smi_clk.s.phase - 3; in octeon_mdio_probe()
200 debug("mdio clock phase: %d clocks\n", smi_clk.s.phase); in octeon_mdio_probe()
/u-boot/tools/dtoc/
A Dtest_src_scan.py247 self.assertEqual('', drv.phase)
283 self.assertEqual('tpl', drv.phase)
386 def setup_dup_drivers(self, name, phase=''): argument
408 ''' % (name, 'DM_PHASE(%s)' % phase if phase else '')
421 scan = src_scan.Scanner(None, None, phase)
442 self.assertEqual('', drv1.phase)
451 self.assertEqual('', drv2.phase)
470 self.assertEqual('spl', drv1.phase)
/u-boot/include/
A Dsym53c8xx.h525 #define WHEN(phase) (0x00030000 | (phase)) argument
526 #define IF(phase) (0x00020000 | (phase)) argument
A Dscsi_emul.h41 enum scsi_cmd_phase phase; member
A Dspl.h178 static inline const char *spl_phase_name(enum u_boot_phase phase) in spl_phase_name() argument
180 switch (phase) { in spl_phase_name()
201 static inline const char *spl_phase_prefix(enum u_boot_phase phase) in spl_phase_prefix() argument
203 switch (phase) { in spl_phase_prefix()
/u-boot/arch/sandbox/dts/
A Dsandbox_vpl.dtsi30 phase = "spl";
45 phase = "u-boot";
/u-boot/doc/device-tree-bindings/sysinfo/
A Dgoogle,coral.txt12 - phase-enforce-gpios: GPIO to indicate the board is in final ship mode
25 phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>;
/u-boot/arch/x86/lib/fsp1/
A Dfsp_support.c169 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) in fsp_notify() argument
185 params.phase = phase; in fsp_notify()
/u-boot/boot/
A Dvbe_simple_fw.c49 enum image_phase_t phase; in vbe_simple_read_bootflow_fw() local
93 phase = IS_ENABLED(CONFIG_VPL_BUILD) ? IH_PHASE_SPL : IH_PHASE_U_BOOT; in vbe_simple_read_bootflow_fw()
105 IH_ARCH_SANDBOX, image_ph(phase, IH_TYPE_FIRMWARE), in vbe_simple_read_bootflow_fw()

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