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Searched refs:phy_addr (Results 1 – 25 of 72) sorted by relevance

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/u-boot/drivers/net/phy/
A Dmv88e6352.c35 static int sw_wait_rdy(const char *devname, u8 phy_addr) in sw_wait_rdy() argument
65 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_read()
76 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_read()
80 ret = miiphy_read(devname, phy_addr, DATA_REG, data); in sw_reg_read()
91 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_write()
107 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_write()
180 ret = ppu_disable(devname, phy_addr); in mv88e_sw_program()
187 ret = sw_reg_write(devname, phy_addr, regs[i].port, in mv88e_sw_program()
191 ppu_enable(devname, phy_addr); in mv88e_sw_program()
197 ret = ppu_enable(devname, phy_addr); in mv88e_sw_program()
[all …]
A Dca_phy.c26 u8 phy_addr; in __internal_phy_init() local
30 for (phy_addr = 4; phy_addr > 0; phy_addr--) { in __internal_phy_init()
31 phydev->addr = phy_addr; in __internal_phy_init()
42 for (phy_addr = 1; phy_addr < 5; phy_addr++) { in __internal_phy_init()
44 phydev->addr = phy_addr; in __internal_phy_init()
54 __func__, phy_addr, data); in __internal_phy_init()
/u-boot/board/freescale/t104xrdb/
A Deth.c24 int phy_addr = 0; in board_eth_init() local
48 phy_addr = CFG_SYS_SGMII1_PHY_ADDR; in board_eth_init()
50 phy_addr = CFG_SYS_SGMII2_PHY_ADDR; in board_eth_init()
52 phy_addr = CFG_SYS_SGMII3_PHY_ADDR; in board_eth_init()
53 fm_info_set_phy_address(i, phy_addr); in board_eth_init()
61 phy_addr = CFG_SYS_RGMII1_PHY_ADDR; in board_eth_init()
63 phy_addr = CFG_SYS_RGMII2_PHY_ADDR; in board_eth_init()
64 fm_info_set_phy_address(i, phy_addr); in board_eth_init()
/u-boot/drivers/net/ti/
A Ddavinci_emac.c63 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) argument
75 static int gen_init_phy(int phy_addr);
77 static int gen_get_link_speed(int phy_addr);
78 static int gen_auto_negotiate(int phy_addr);
220 ((phy_addr & 0x1f) << 16), in davinci_eth_phy_read()
245 ((phy_addr & 0x1f) << 16) | in davinci_eth_phy_write()
257 static int gen_init_phy(int phy_addr) in gen_init_phy() argument
261 if (gen_get_link_speed(phy_addr)) { in gen_init_phy()
263 ret = gen_get_link_speed(phy_addr); in gen_init_phy()
287 static int gen_get_link_speed(int phy_addr) in gen_get_link_speed() argument
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A Ddavinci_emac.h293 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
294 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
298 int (*init)(int phy_addr);
299 int (*is_phy_connected)(int phy_addr);
300 int (*get_link_speed)(int phy_addr);
301 int (*auto_negotiate)(int phy_addr);
/u-boot/arch/mips/mach-octeon/
A Dcvmx-helper-board.c675 u32 phy_addr = phy_info->phy_addr; in __get_marvell_phy_link_state() local
679 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, 22, 0); in __get_marvell_phy_link_state()
689 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0); in __get_marvell_phy_link_state()
726 u32 phy_addr = phy_info->phy_addr; in __get_broadcom_phy_link_state() local
789 u32 phy_addr = phy_info->phy_addr; in __cvmx_get_generic_8023_c22_phy_link_state() local
808 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0xA); in __cvmx_get_generic_8023_c22_phy_link_state()
810 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x9); in __cvmx_get_generic_8023_c22_phy_link_state()
814 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x5); in __cvmx_get_generic_8023_c22_phy_link_state()
816 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x4); in __cvmx_get_generic_8023_c22_phy_link_state()
848 u32 phy_addr = phy_info->phy_addr; in __cvmx_get_qualcomm_s17_phy_link_state() local
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A Dcvmx-bootmem.c803 CAST_ULL(phy_addr), CAST_ULL(size)); in __cvmx_bootmem_phy_free()
809 if (!size || !phy_addr) in __cvmx_bootmem_phy_free()
822 else if (phy_addr + size == cur_addr) { in __cvmx_bootmem_phy_free()
824 cvmx_bootmem_phy_set_next(phy_addr, in __cvmx_bootmem_phy_free()
826 cvmx_bootmem_phy_set_size(phy_addr, in __cvmx_bootmem_phy_free()
842 while (cur_addr && phy_addr > cur_addr) { in __cvmx_bootmem_phy_free()
858 cvmx_bootmem_phy_set_next(phy_addr, 0); in __cvmx_bootmem_phy_free()
871 if (phy_addr + size == cur_addr) { in __cvmx_bootmem_phy_free()
881 } else if (phy_addr + size == cur_addr) { in __cvmx_bootmem_phy_free()
883 cvmx_bootmem_phy_set_size(phy_addr, in __cvmx_bootmem_phy_free()
[all …]
/u-boot/drivers/net/pfe_eth/
A Dpfe_mdio.c19 static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr, in pfe_write_addr() argument
29 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT); in pfe_write_addr()
53 static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, in pfe_phy_read() argument
67 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_read()
72 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT); in pfe_phy_read()
103 phy_addr, reg_addr, val); in pfe_phy_read()
108 static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, in pfe_phy_write() argument
121 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_write()
126 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT); in pfe_phy_write()
152 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr, in pfe_phy_write()
/u-boot/drivers/net/octeon/
A Docteon_mdio.c56 static int octeon_mdio_read(struct udevice *mdio_dev, int phy_addr, in octeon_mdio_read() argument
64 dev, dev->name, p->bus_id, phy_addr, dev_addr, reg_addr); in octeon_mdio_read()
67 value = cvmx_mdio_45_read(p->bus_id & 0xff, phy_addr, dev_addr, in octeon_mdio_read()
70 value = cvmx_mdio_read(p->bus_id & 0xff, phy_addr, reg_addr); in octeon_mdio_read()
77 static int octeon_mdio_write(struct udevice *mdio_dev, int phy_addr, in octeon_mdio_write() argument
84 __func__, dev, dev->name, p->bus_id, phy_addr, dev_addr, reg_addr, in octeon_mdio_write()
89 return cvmx_mdio_45_write(p->bus_id & 0xff, phy_addr, dev_addr, in octeon_mdio_write()
93 return cvmx_mdio_write(p->bus_id & 0xff, phy_addr, reg_addr, value); in octeon_mdio_write()
/u-boot/drivers/net/
A Dmcfmii.c132 return info->phy_addr; in mii_discover_phy()
225 info->phy_addr = mii_discover_phy(info); in mii_init()
227 if (info->phy_addr == -1) in mii_init()
234 miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status); in mii_init()
245 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status); in mii_init()
255 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; in mii_init()
256 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); in mii_init()
A Dmtk_eth.c122 int phy_addr; member
411 u8 phy_addr; in mt7531_mii_ind_read() local
425 u8 phy_addr; in mt7531_mii_ind_write() local
438 u8 phy_addr; in mt7531_mmd_ind_read() local
458 u8 phy_addr; in mt7531_mmd_ind_write() local
546 return priv->mmd_read(priv, phy_addr, 0x1f, reg); in mt753x_core_reg_read()
553 priv->mmd_write(priv, phy_addr, 0x1f, reg, val); in mt753x_core_reg_write()
618 u16 phy_addr, phy_val; in mt7530_setup() local
645 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7530_setup()
828 u16 phy_addr, phy_val; in mt7531_setup() local
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A Dsni_netsec.c272 u32 phy_addr, freq; member
449 int phy_addr, int reg_addr) in netsec_get_phy_reg() argument
454 if (phy_addr != 7) in netsec_get_phy_reg()
458 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | in netsec_get_phy_reg()
477 int phy_addr, int reg_addr, u16 val) in netsec_set_phy_reg() argument
481 if (phy_addr != 7) in netsec_set_phy_reg()
487 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | in netsec_set_phy_reg()
504 netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1); in netsec_set_phy_reg()
712 int phy_addr, int devad, int reg_addr) in _netsec_get_phy_reg() argument
718 int phy_addr, int devad, int reg_addr, u16 val) in _netsec_set_phy_reg() argument
[all …]
A Dmt7620-eth.c233 int phy_addr; member
563 if (priv->port_cfg[0].phy_addr > 0) in mt7620_gsw_ephy_init()
566 if (priv->port_cfg[1].phy_addr > 0) in mt7620_gsw_ephy_init()
674 if (priv->port_cfg[0].phy_addr < 0 && priv->port_cfg[1].phy_addr < 0) in mt7620_gsw_setup_phy_polling()
677 if (priv->port_cfg[0].phy_addr > 0 && priv->port_cfg[1].phy_addr > 0) { in mt7620_gsw_setup_phy_polling()
678 phy_addr_st = priv->port_cfg[0].phy_addr; in mt7620_gsw_setup_phy_polling()
1052 u32 phy_addr; in mt7620_eth_parse_gsw_port() local
1105 if (phy_addr > 31 || (idx == 0 && phy_addr < 3) || in mt7620_eth_parse_gsw_port()
1106 (idx == 1 && phy_addr < 4)) { in mt7620_eth_parse_gsw_port()
1111 priv->port_cfg[idx].phy_addr = phy_addr; in mt7620_eth_parse_gsw_port()
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A Dftgmac100.c86 u32 phy_addr; member
102 static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr, in ftgmac100_mdio_read() argument
112 FTGMAC100_PHYCR_PHYAD(phy_addr) | in ftgmac100_mdio_read()
122 bus->name, phy_addr, reg_addr); in ftgmac100_mdio_read()
131 static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr, in ftgmac100_mdio_write() argument
141 FTGMAC100_PHYCR_PHYAD(phy_addr) | in ftgmac100_mdio_write()
154 bus->name, phy_addr, reg_addr); in ftgmac100_mdio_write()
226 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); in ftgmac100_phy_init()
583 priv->phy_addr = 0; in ftgmac100_probe()
589 priv->phy_addr = CONFIG_PHY_ADDR; in ftgmac100_probe()
/u-boot/drivers/phy/marvell/
A Dcomphy_a3700.c178 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); in comphy_pcie_power_up()
193 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); in comphy_pcie_power_up()
203 reg_set16(phy_addr(PCIE, MISC_REG0), in comphy_pcie_power_up()
217 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); in comphy_pcie_power_up()
220 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); in comphy_pcie_power_up()
233 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); in comphy_pcie_power_up()
235 reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv); in comphy_pcie_power_up()
238 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); in comphy_pcie_power_up()
240 reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv); in comphy_pcie_power_up()
245 reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0), in comphy_pcie_power_up()
[all …]
/u-boot/net/
A Dmdio-uclass.c140 u32 phy_addr; in dm_phy_find_by_ofnode() local
142 if (ofnode_read_u32(phynode, "reg", &phy_addr)) in dm_phy_find_by_ofnode()
155 return phy_find_by_mask(pdata->mii_bus, BIT(phy_addr)); in dm_phy_find_by_ofnode()
173 u32 phy_addr; in dm_eth_connect_phy_handle() local
194 if (ofnode_read_u32(phynode, "reg", &phy_addr)) { in dm_eth_connect_phy_handle()
207 phy = dm_mdio_phy_connect(mdiodev, phy_addr, ethdev, interface); in dm_eth_connect_phy_handle()
/u-boot/include/
A Dmv88e6352.h71 int mv88e_sw_reset(const char *devname, u8 phy_addr);
72 int mv88e_sw_program(const char *devname, u8 phy_addr,
A Dnetdev.h39 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
54 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
59 int phy_addr);
/u-boot/drivers/net/ldpaa_eth/
A Dldpaa_wriop.c39 dpmac_info[dpmac_id].phy_addr[phy_num] = -1; in wriop_init_dpmac()
52 dpmac_info[dpmac_id].phy_addr[phy_num] = -1; in wriop_init_dpmac_enet_if()
138 dpmac_info[i].phy_addr[phy_num] = address; in wriop_set_phy_address()
152 return dpmac_info[i].phy_addr[phy_num]; in wriop_get_phy_address()
/u-boot/drivers/net/octeontx/
A Dsmi.c263 int rxaui_phy_xs_init(struct mii_dev *bus, int phy_addr) in rxaui_phy_xs_init() argument
270 phy_id1 = octeontx_phy_read(bus, phy_addr, 1, 0x2); in rxaui_phy_xs_init()
271 phy_id2 = octeontx_phy_read(bus, phy_addr, 1, 0x3); in rxaui_phy_xs_init()
283 reg = octeontx_phy_read(bus, phy_addr, 4, 0x0); in rxaui_phy_xs_init()
287 octeontx_phy_write(bus, phy_addr, 4, 0x0, reg); in rxaui_phy_xs_init()
291 reg = octeontx_phy_read(bus, phy_addr, 4, 0x0); in rxaui_phy_xs_init()
301 octeontx_phy_write(bus, phy_addr, 4, 0xc003, 0x5); in rxaui_phy_xs_init()
/u-boot/drivers/net/mscc_eswitch/
A Dservalt_switch.c118 size_t phy_addr; member
404 size_t phy_addr, struct mii_dev *bus) in add_port_entry() argument
406 priv->ports[index].phy_addr = phy_addr; in add_port_entry()
418 size_t phy_addr; in servalt_probe() local
456 phy_addr = res.start; in servalt_probe()
475 add_port_entry(priv, i, phy_addr, bus); in servalt_probe()
484 phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev, in servalt_probe()
A Docelot_switch.c154 size_t phy_addr; member
514 size_t phy_addr, struct mii_dev *bus, in add_port_entry() argument
517 priv->ports[index].phy_addr = phy_addr; in add_port_entry()
536 size_t phy_addr; in ocelot_probe() local
573 phy_addr = res.start; in ocelot_probe()
597 add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff); in ocelot_probe()
599 add_port_entry(priv, i, phy_addr, bus, phandle.args[1], in ocelot_probe()
610 priv->ports[i].phy_addr, dev, in ocelot_probe()
/u-boot/board/ti/am335x/
A Dboard.c630 int phy_addr; in ft_board_setup() local
655 phy_addr = cpsw_get_slave_phy_addr(ethdev, i); in ft_board_setup()
661 if (phy_id[1] != phy_addr) { in ft_board_setup()
663 alias, phy_id[1], phy_addr); in ft_board_setup()
666 phy_id[1] = cpu_to_fdt32(phy_addr); in ft_board_setup()
680 if (ret != phy_addr) { in ft_board_setup()
682 alias, ret, phy_addr); in ft_board_setup()
685 cpu_to_fdt32(phy_addr)); in ft_board_setup()
909 .phy_addr = 0,
914 .phy_addr = 1,
/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dcpu.c106 static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr) in set_pgtable() argument
108 u32 value = phy_addr | PMD_TYPE_TABLE; in set_pgtable()
115 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() argument
120 value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF; in set_pgsection()
/u-boot/arch/arm/mach-rockchip/
A Dsdram.c25 s64 phy_addr; member
31 s64 phy_addr; member
62 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr in dram_init_banksize()
64 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + in dram_init_banksize()

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