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Searched refs:phy_ctrl (Results 1 – 25 of 29) sorted by relevance

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/u-boot/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c281 *phy_ctrl) in dmc_get_read_offset_value()
283 return readl(&phy_ctrl->phy_con4); in dmc_get_read_offset_value()
293 setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
308 writel(offset, &phy_ctrl->phy_con4); in dmc_set_read_offset_value()
309 ddr_phy_set_do_resync(phy_ctrl); in dmc_set_read_offset_value()
360 dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); in test_shifts()
369 offsetr = dmc_get_read_offset_value(phy_ctrl); in test_shifts()
372 dmc_set_read_offset_value(phy_ctrl, offsetr); in test_shifts()
424 test_shifts(phy_ctrl, ch, left_limit, right_limit, left); in software_find_read_offset()
425 test_shifts(phy_ctrl, ch, right_limit, left_limit, right); in software_find_read_offset()
[all …]
/u-boot/drivers/usb/host/
A Dehci-mx6.c199 void __iomem *phy_ctrl; in usb_phy_enable() local
203 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
218 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
222 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
228 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
238 void __iomem *phy_ctrl; in usb_phy_mode() local
242 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_mode()
244 val = readl(phy_ctrl); in usb_phy_mode()
513 void *__iomem phy_ctrl, *__iomem phy_status; in ehci_usb_phy_mode() local
534 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL); in ehci_usb_phy_mode()
[all …]
A Dehci-vf.c90 void __iomem *phy_ctrl; in usb_phy_enable() local
94 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
107 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
111 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
118 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
/u-boot/drivers/ram/aspeed/
A Dsdram_ast2500.c99 writel(0, &regs->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
102 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
103 while ((readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) in ast2500_ddr_phy_init_process()
106 &regs->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
111 writel(0, &info->regs->phy_ctrl[0]); in ast2500_sdrammc_set_vref()
A Dsdram_ast2600.c559 writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]); in ast2600_sdramphy_kick_training()
561 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]); in ast2600_sdramphy_kick_training()
565 data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; in ast2600_sdramphy_kick_training()
588 writel(0, &info->regs->phy_ctrl[0]); in ast2600_sdramphy_init()
/u-boot/doc/device-tree-bindings/phy/
A Dsun4i-usb-phy.txt18 * "phy_ctrl"
53 reg-names = "phy_ctrl", "pmu1", "pmu2";
/u-boot/arch/arm/include/asm/arch-aspeed/
A Dsdram_ast2500.h120 u32 phy_ctrl[4]; member
A Dsdram_ast2600.h156 u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ member
/u-boot/drivers/net/
A De1000.c2382 uint32_t phy_ctrl = 0; in e1000_set_d3_lplu_state() local
2404 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d3_lplu_state()
2474 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; in e1000_set_d3_lplu_state()
2517 uint32_t phy_ctrl = 0; in e1000_set_d0_lplu_state() local
2526 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d0_lplu_state()
2538 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; in e1000_set_d0_lplu_state()
2539 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
2541 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; in e1000_set_d0_lplu_state()
2586 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; in e1000_set_d0_lplu_state()
2587 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
[all …]
/u-boot/arch/arm/dts/
A Dsun8i-a23.dtsi103 reg-names = "phy_ctrl", "pmu1";
A Dsuniv-f1c100s.dtsi153 reg-names = "phy_ctrl";
A Dsun8i-a33.dtsi431 reg-names = "phy_ctrl", "pmu1";
A Dsun8i-v3s.dtsi312 reg-names = "phy_ctrl",
A Dam33xx.dtsi408 reg-names = "phy_ctrl", "wakeup";
A Dsun50i-h616.dtsi528 reg-names = "phy_ctrl",
A Dsun5i.dtsi383 reg-names = "phy_ctrl", "pmu1";
A Dsunxi-h3-h5.dtsi274 reg-names = "phy_ctrl",
A Dsun50i-h6.dtsi683 reg-names = "phy_ctrl",
A Dsun4i-a10.dtsi506 reg-names = "phy_ctrl", "pmu1", "pmu2";
A Dsun8i-a83t.dtsi643 reg-names = "phy_ctrl",
A Dsun50i-a64.dtsi594 reg-names = "phy_ctrl",
A Dsun6i-a31.dtsi527 reg-names = "phy_ctrl",
/u-boot/drivers/ram/
A Dk3-am654-ddrss.c207 struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl; in am654_ddrss_phy_configuration()
1016 (u32 *)&ddrss->params.phy_ctrl, in am654_ddrss_ofdata_to_priv()
1017 sizeof(ddrss->params.phy_ctrl) / sizeof(u32)); in am654_ddrss_ofdata_to_priv()
A Dk3-am654-ddrss.h1194 struct ddrss_ddrphy_ctrl_params phy_ctrl; member
/u-boot/arch/arm/mach-exynos/include/mach/
A Ddp.h192 unsigned int phy_ctrl; member

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