Home
last modified time | relevance | path

Searched refs:phys (Results 1 – 25 of 336) sorted by relevance

12345678910>>...14

/u-boot/arch/arm/mach-k3/
A Darm64-mmu.c24 .phys = 0x0UL,
31 .phys = 0x80000000UL,
37 .phys = 0xa0000000UL,
43 .phys = 0xa2100000UL,
49 .phys = 0x880000000UL,
55 .phys = 0x500000000UL,
79 .phys = 0x0UL,
86 .phys = 0x80000000UL,
137 .phys = 0x0UL,
191 .phys = 0x0UL,
[all …]
/u-boot/arch/arm/mach-apple/
A Dboard.c25 .phys = 0x200000000,
33 .phys = 0x380000000,
41 .phys = 0x500000000,
49 .phys = 0x680000000,
57 .phys = 0x6a0000000,
65 .phys = 0x6c0000000,
73 .phys = 0x800000000,
94 .phys = 0x280000000,
102 .phys = 0x380000000,
110 .phys = 0x580000000,
[all …]
/u-boot/drivers/net/
A Dmdio_mux_meson_g12a.c53 phys_addr_t phys; member
59 writel(0x29c0040a, priv->phys + ETH_PLL_CTL0); in meson_g12a_ephy_pll_init()
60 writel(0x927e0000, priv->phys + ETH_PLL_CTL1); in meson_g12a_ephy_pll_init()
61 writel(0xac5f49e5, priv->phys + ETH_PLL_CTL2); in meson_g12a_ephy_pll_init()
62 writel(0x00000000, priv->phys + ETH_PLL_CTL3); in meson_g12a_ephy_pll_init()
63 writel(0x00000000, priv->phys + ETH_PLL_CTL4); in meson_g12a_ephy_pll_init()
64 writel(0x20200000, priv->phys + ETH_PLL_CTL5); in meson_g12a_ephy_pll_init()
83 priv->phys + ETH_PHY_CNTL1); in meson_g12a_enable_internal_mdio()
87 priv->phys + ETH_PHY_CNTL2); in meson_g12a_enable_internal_mdio()
95 writel(0x0, priv->phys + ETH_PHY_CNTL2); in meson_g12a_enable_external_mdio()
[all …]
A Dmdio_mux_mmioreg.c18 phys_addr_t phys; member
37 x = ioread8((void *)priv->phys); in mdio_mux_mmioreg_select()
40 iowrite8((x & ~priv->mask) | sel, (void *)priv->phys); in mdio_mux_mmioreg_select()
49 x = ioread16((void *)priv->phys); in mdio_mux_mmioreg_select()
52 iowrite16((x & ~priv->mask) | sel, (void *)priv->phys); in mdio_mux_mmioreg_select()
61 x = ioread32((void *)priv->phys); in mdio_mux_mmioreg_select()
64 iowrite32((x & ~priv->mask) | sel, (void *)priv->phys); in mdio_mux_mmioreg_select()
108 priv->phys = reg_base; in mdio_mux_mmioreg_probe()
/u-boot/arch/mips/dts/
A Djr2_pcb111.dts241 phys = <&serdes_hsio 1 0xff PHY_MODE_QSGMII>;
246 phys = <&serdes_hsio 2 0xff PHY_MODE_QSGMII>;
251 phys = <&serdes_hsio 3 0xff PHY_MODE_QSGMII>;
261 phys = <&serdes_hsio 5 0xff PHY_MODE_QSGMII>;
266 phys = <&serdes_hsio 6 0xff PHY_MODE_QSGMII>;
271 phys = <&serdes_hsio 7 0xff PHY_MODE_QSGMII>;
281 phys = <&serdes_hsio 9 0xff PHY_MODE_QSGMII>;
286 phys = <&serdes_hsio 10 0xff PHY_MODE_QSGMII>;
291 phys = <&serdes_hsio 11 0xff PHY_MODE_QSGMII>;
301 phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
[all …]
A Dluton_pcb090.dts194 phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>;
199 phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
204 phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
209 phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
214 phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>;
219 phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
224 phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
229 phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
239 phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
244 phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
[all …]
A Djr2_pcb110.dts112 phys = <&serdes_hsio 0 SERDES1G(1) PHY_MODE_SGMII>;
117 phys = <&serdes_hsio 1 SERDES1G(2) PHY_MODE_SGMII>;
122 phys = <&serdes_hsio 2 SERDES1G(3) PHY_MODE_SGMII>;
127 phys = <&serdes_hsio 3 SERDES1G(4) PHY_MODE_SGMII>;
132 phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
137 phys = <&serdes_hsio 5 SERDES1G(6) PHY_MODE_SGMII>;
142 phys = <&serdes_hsio 6 SERDES1G(7) PHY_MODE_SGMII>;
147 phys = <&serdes_hsio 7 SERDES1G(8) PHY_MODE_SGMII>;
/u-boot/arch/arm/mach-exynos/
A Dmmu-arm64.c15 .phys = 0x10000000UL,
22 .phys = 0x40000000UL,
38 .phys = 0x10000000UL,
46 .phys = 0x40000000UL,
53 .phys = 0x80000000UL,
71 .phys = 0x10000000UL,
79 .phys = 0x40000000UL,
86 .phys = 0x80000000UL,
/u-boot/arch/arm/mach-socfpga/
A Dmmu-arm64_s10.c17 .phys = 0x0UL,
24 .phys = 0x80000000UL,
32 .phys = 0xF7000000UL,
40 .phys = 0xFFE00000UL,
47 .phys = 0xFFFC0000UL,
55 .phys = 0x0100000000UL,
62 .phys = 0x2000000000UL,
/u-boot/drivers/pci/
A Dpcie_layerscape_ep.c73 u64 phys = 0; in ls_pcie_ep_setup_atu() local
77 phys = ALIGN(phys, PCIE_BAR0_SIZE); in ls_pcie_ep_setup_atu()
80 0 + pf * BAR_NUM, 0, phys); in ls_pcie_ep_setup_atu()
82 phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE); in ls_pcie_ep_setup_atu()
84 1 + pf * BAR_NUM, 1, phys); in ls_pcie_ep_setup_atu()
86 phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE); in ls_pcie_ep_setup_atu()
90 phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR4_SIZE); in ls_pcie_ep_setup_atu()
97 phys = ALIGN(phys + PCIE_BAR4_SIZE, PCIE_BAR0_SIZE); in ls_pcie_ep_setup_atu()
101 phys = ALIGN(phys + PCIE_BAR0_SIZE * PCIE_VF_NUM, in ls_pcie_ep_setup_atu()
106 phys = ALIGN(phys + PCIE_BAR1_SIZE * PCIE_VF_NUM, in ls_pcie_ep_setup_atu()
[all …]
/u-boot/arch/arm/mach-rmobile/
A Dmemmap-gen3.c18 .phys = 0x0UL,
25 .phys = 0x40000000UL,
31 .phys = 0x47E00000UL,
37 .phys = 0xc0000000UL,
44 .phys = 0x100000000UL,
65 gen3_mem_map[i].phys = 0x0ULL; in enable_caches()
89 gen3_mem_map[i].phys = 0x40000000ULL; in enable_caches()
100 gen3_mem_map[i].phys = start; in enable_caches()
109 gen3_mem_map[i].phys = 0xc0000000ULL; in enable_caches()
130 gen3_mem_map[i].phys = start; in enable_caches()
[all …]
/u-boot/board/armltd/corstone1000/
A Dcorstone1000.c20 .phys = 0x02000000UL,
27 .phys = 0x08000000UL,
34 .phys = 0x1A000000UL,
42 .phys = 0x40200000UL,
50 .phys = 0x40100000UL,
58 .phys = 0x80000000UL,
/u-boot/include/
A Dphys2bus.h10 unsigned long phys_to_bus(unsigned long phys);
13 static inline unsigned long phys_to_bus(unsigned long phys) in phys_to_bus() argument
15 return phys; in phys_to_bus()
27 static inline dma_addr_t dev_phys_to_bus(struct udevice *dev, phys_addr_t phys) in dev_phys_to_bus() argument
29 return phys - dev_get_dma_offset(dev); in dev_phys_to_bus()
A Ddwc3-uboot.h51 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys);
52 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys);
54 static inline int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys) in dwc3_setup_phy() argument
59 static inline int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys) in dwc3_shutdown_phy() argument
/u-boot/test/dm/
A Dphy.c132 struct phy_bulk phys; in dm_test_phy_bulk() local
139 ut_assertok(generic_phy_get_bulk(parent, &phys)); in dm_test_phy_bulk()
140 ut_asserteq(2, phys.count); in dm_test_phy_bulk()
142 ut_asserteq(0, generic_phy_init_bulk(&phys)); in dm_test_phy_bulk()
143 ut_asserteq(0, generic_phy_power_on_bulk(&phys)); in dm_test_phy_bulk()
144 ut_asserteq(0, generic_phy_power_off_bulk(&phys)); in dm_test_phy_bulk()
145 ut_asserteq(0, generic_phy_exit_bulk(&phys)); in dm_test_phy_bulk()
151 ut_assertok(generic_phy_get_bulk(parent, &phys)); in dm_test_phy_bulk()
152 ut_asserteq(3, phys.count); in dm_test_phy_bulk()
154 ut_asserteq(0, generic_phy_init_bulk(&phys)); in dm_test_phy_bulk()
[all …]
/u-boot/drivers/usb/dwc3/
A Ddwc3-meson-gxl.c115 struct phy phys[PHY_COUNT]; member
159 if (!priv->phys[i].dev) in dwc3_meson_gxl_usb2_init()
207 if (!priv->phys[USB2_OTG_PHY].dev) in dwc3_meson_gxl_force_mode()
241 &priv->phys[i]); in dwc3_meson_gxl_get_phys()
243 priv->phys[i].dev = NULL; in dwc3_meson_gxl_get_phys()
349 if (!priv->phys[i].dev) in dwc3_meson_gxl_probe()
358 if (!priv->phys[i].dev) in dwc3_meson_gxl_probe()
366 if (priv->phys[USB2_OTG_PHY].dev) in dwc3_meson_gxl_probe()
376 if (!priv->phys[i].dev) in dwc3_meson_gxl_probe()
395 if (!priv->phys[i].dev) in dwc3_meson_gxl_remove()
[all …]
/u-boot/arch/arm/mach-versal-net/
A Dcpu.c32 .phys = 0x80000000UL,
39 .phys = 0xf0000000UL,
46 .phys = 0x400000000UL,
53 .phys = 0x600000000UL,
59 .phys = 0xe00000000UL,
77 versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; in mem_map_fill()
/u-boot/arch/arm/mach-snapdragon/
A Dsysmap-qcs404.c14 .phys = 0x0UL, /* Peripheral block */
21 .phys = 0x80000000UL, /* DDR */
27 .phys = 0x89600000UL, /* DDR */
33 .phys = 0xa0000000UL, /* DDR */
/u-boot/arch/arm/mach-octeontx2/
A Dcpu.c24 .phys = 0x800000000000UL,
30 .phys = 0x840000000000UL,
36 .phys = 0x880000000000UL,
42 .phys = 0x8c0000000000UL,
58 otx2_mem_map[banks].phys = dram_start; in mem_map_fill()
/u-boot/arch/arm/mach-versal/
A Dcpu.c36 .phys = 0x80000000UL,
43 .phys = 0xf0000000UL,
50 .phys = 0x400000000UL,
57 .phys = 0x600000000UL,
63 .phys = 0xe00000000UL,
77 versal_mem_map[banks].phys = 0xffe00000UL; in mem_map_fill()
99 versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; in mem_map_fill()
/u-boot/arch/arm/mach-octeontx/
A Dcpu.c24 .phys = 0x800000000000UL,
30 .phys = 0x840000000000UL,
36 .phys = 0x880000000000UL,
53 otx_mem_map[banks].phys = 0x8c0000000000UL; in mem_map_fill()
62 otx_mem_map[banks].phys = dram_start; in mem_map_fill()
/u-boot/arch/arm/mach-bcm283x/
A Dphys2bus.c9 unsigned long phys_to_bus(unsigned long phys) in phys_to_bus() argument
12 return 0xc0000000 | phys; in phys_to_bus()
14 return 0x40000000 | phys; in phys_to_bus()
A Dinit.c27 .phys = 0x00000000UL,
33 .phys = 0x3f000000UL,
47 .phys = 0x00000000UL,
53 .phys = 0xfc000000UL,
60 .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
90 mem_map[i].phys = pd[i].phys; in _rpi_update_mem_map()
/u-boot/arch/arm/mach-mvebu/alleycat5/
A Dcpu.c24 .phys = CFG_SYS_SDRAM_BASE,
31 .phys = 0x00000000,
41 .phys = 0x100000,
51 .phys = 0x7F000000,
/u-boot/arch/arm/mach-uniphier/arm64/
A Dmem_map.c14 .phys = 0x00000000,
22 .phys = 0x80000000,
36 uniphier_mem_map[1].phys = dram_base; in uniphier_mem_map_init()

Completed in 45 milliseconds

12345678910>>...14