Home
last modified time | relevance | path

Searched refs:pin (Results 1 – 25 of 570) sorted by relevance

12345678910>>...23

/u-boot/arch/arm/dts/
A Ds5p4418-pinctrl.dtsi3 * Nexell's s5p6818 SoC pin-mux and pin-config device tree source
10 * Nexell's s5p6818 SoC pin-mux and pin-config options are listed as
26 pin-pull = <2>;
33 pin-pull = <2>;
40 pin-pull = <2>;
47 pin-pull = <2>;
54 pin-pull = <2>;
61 pin-pull = <2>;
68 pin-pull = <2>;
75 pin-pull = <2>;
[all …]
A Dsama5d3_lcd.dtsi42 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
44 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
45 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
46 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
47 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
48 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
49 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
50 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
51 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
A Dexynos78x0-pinctrl.dtsi3 * Samsung's Exynos7880 SoC pin-mux and pin-config device tree source
9 * Samsung's Exynos7880 SoC pin-mux and pin-config options are listed as device
23 samsung,pin-pud = <0>;
29 samsung,pin-pud = <0>;
30 samsung,pin-drv = <4>;
36 samsung,pin-pud = <0>;
37 samsung,pin-drv = <0>;
43 samsung,pin-pud = <0>;
44 samsung,pin-drv = <0>;
50 samsung,pin-pud = <0>;
[all …]
A Dat91sam9x5_lcd.dtsi42 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
44 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
45 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
46 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
47 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
48 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
49 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
50 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
51 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
/u-boot/drivers/gpio/
A Dkw_gpio.c30 u |= 1 << (pin & 31); in __set_direction()
32 u &= ~(1 << (pin & 31)); in __set_direction()
42 u = readl(GPIO_OUT(pin)); in __set_level()
44 u |= 1 << (pin & 31); in __set_level()
46 u &= ~(1 << (pin & 31)); in __set_level()
47 writel(u, GPIO_OUT(pin)); in __set_level()
56 u |= 1 << (pin & 31); in __set_blinking()
64 if (pin < GPIO_MAX) { in kw_gpio_is_valid()
128 if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31))) in kw_gpio_get_value()
129 val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin)); in kw_gpio_get_value()
[all …]
A Dnx_gpio.c74 setbits_le32(&regs->data, 1 << pin); in nx_alive_gpio_direction_output()
78 setbits_le32(&regs->outputenb, 1 << pin); in nx_alive_gpio_direction_output()
87 unsigned int mask = 1UL << pin; in nx_alive_gpio_get_value()
102 setbits_le32(&regs->data, 1 << pin); in nx_alive_gpio_set_value()
113 unsigned int mask = (1UL << pin); in nx_alive_gpio_get_function()
147 setbits_le32(&regs->data, 1 << pin); in nx_gpio_direction_output()
149 clrbits_le32(&regs->data, 1 << pin); in nx_gpio_direction_output()
160 unsigned int mask = 1UL << pin; in nx_gpio_get_value()
180 setbits_le32(&regs->data, 1 << pin); in nx_gpio_set_value()
182 clrbits_le32(&regs->data, 1 << pin); in nx_gpio_set_value()
[all …]
A Dat91_gpio.c78 mask = 1 << pin; in at91_set_pio_periph()
96 mask = 1 << pin; in at91_set_a_periph()
115 mask = 1 << pin; in at91_set_b_periph()
134 mask = 1 << pin; in at91_pio3_set_a_periph()
157 mask = 1 << pin; in at91_pio3_set_b_periph()
179 mask = 1 << pin; in at91_pio3_set_c_periph()
201 mask = 1 << pin; in at91_pio3_set_d_periph()
290 mask = 1 << pin; in at91_set_pio_deglitch()
309 mask = 1 << pin; in at91_pio3_set_pio_deglitch()
330 mask = 1 << pin; in at91_pio3_set_pio_debounce()
[all …]
A Daxp_gpio.c20 static u8 axp_get_gpio_ctrl_reg(unsigned pin) in axp_get_gpio_ctrl_reg() argument
22 switch (pin) { in axp_get_gpio_ctrl_reg()
39 reg = axp_get_gpio_ctrl_reg(pin); in axp_gpio_direction_input()
52 switch (pin) { in axp_gpio_direction_output()
61 return axp_gpio_set_value(dev, pin, val); in axp_gpio_direction_output()
64 reg = axp_get_gpio_ctrl_reg(pin); in axp_gpio_direction_output()
78 switch (pin) { in axp_gpio_get_value()
87 reg = axp_get_gpio_ctrl_reg(pin); in axp_gpio_get_value()
92 mask = 1 << (pin + AXP_GPIO_STATE_OFFSET); in axp_gpio_get_value()
104 switch (pin) { in axp_gpio_set_value()
[all …]
/u-boot/arch/arm/mach-kirkwood/include/mach/
A Dgpio.h18 #define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) argument
19 #define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) argument
20 #define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) argument
21 #define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) argument
22 #define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) argument
23 #define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) argument
24 #define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) argument
25 #define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) argument
26 #define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) argument
36 int kw_gpio_get_value(unsigned pin);
[all …]
/u-boot/board/sunxi/
A Dboard.c319 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) in nand_pinmux_setup()
323 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) in nand_pinmux_setup()
361 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { in mmc_pinmux_setup()
380 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { in mmc_pinmux_setup()
388 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { in mmc_pinmux_setup()
395 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { in mmc_pinmux_setup()
402 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { in mmc_pinmux_setup()
413 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { in mmc_pinmux_setup()
420 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { in mmc_pinmux_setup()
449 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { in mmc_pinmux_setup()
[all …]
/u-boot/drivers/pinctrl/renesas/
A DKconfig4 bool "Renesas pin control drivers"
8 Support pin multiplexing control on Renesas SoCs.
15 bool "Renesas RCar Gen2 R8A7790 pin control driver"
21 bool "Renesas RCar Gen2 R8A7791 pin control driver"
27 bool "Renesas RCar Gen2 R8A7792 pin control driver"
33 bool "Renesas RCar Gen2 R8A7793 pin control driver"
39 bool "Renesas RCar Gen2 R8A7794 pin control driver"
69 bool "Renesas RCar Gen3 R8A7795 pin control driver"
75 bool "Renesas RCar Gen3 R8A77960 pin control driver"
135 bool "Renesas RZ/A1 R7S72100 pin control driver"
[all …]
/u-boot/board/LaCie/common/
A Dcpld-gpio-bus.c19 int pin; in cpld_gpio_bus_set_addr() local
21 for (pin = 0; pin < bus->num_addr; pin++) in cpld_gpio_bus_set_addr()
22 kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1); in cpld_gpio_bus_set_addr()
27 int pin; in cpld_gpio_bus_set_data() local
29 for (pin = 0; pin < bus->num_data; pin++) in cpld_gpio_bus_set_data()
30 kw_gpio_set_value(bus->data[pin], (data >> pin) & 1); in cpld_gpio_bus_set_data()
/u-boot/arch/arm/mach-tegra/
A Dpinmux-common.c13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT)) argument
96 #define REG(pin) _R(0x3000 + ((pin) * 4)) argument
98 #define MUX_REG(pin) REG(pin) argument
101 #define PULL_REG(pin) REG(pin) argument
104 #define TRI_REG(pin) REG(pin) argument
235 u32 *reg = REG(pin); in pinmux_set_io()
257 u32 *reg = REG(pin); in pinmux_set_lock()
284 u32 *reg = REG(pin); in pinmux_set_od()
309 u32 *reg = REG(pin); in pinmux_set_ioreset()
334 u32 *reg = REG(pin); in pinmux_set_rcv_sel()
[all …]
/u-boot/drivers/pinctrl/rockchip/
A Dpinctrl-rk3308.c19 .pin = 14,
25 .pin = 15,
31 .pin = 18,
37 .pin = 19,
43 .pin = 20,
49 .pin = 21,
55 .pin = 22,
61 .pin = 23,
67 .pin = 12,
79 .pin = 2,
[all …]
A Dpinctrl-rockchip-core.c52 data->pin == pin) in rockchip_get_recalced_mux()
76 data->pin == pin && data->func == mux) in rockchip_get_mux_route()
94 if ((pin % 8) >= 4) in rockchip_get_mux_data()
96 *bit = (pin % 4) * 4; in rockchip_get_mux_data()
103 if ((pin % 8) >= 5) in rockchip_get_mux_data()
105 *bit = (pin % 8 % 5) * 3; in rockchip_get_mux_data()
108 *bit = (pin % 8) * 2; in rockchip_get_mux_data()
590 int pin = 0; in rockchip_pinctrl_get_soc_data() local
593 pin = ctrl->iomux_recalced[j].pin; in rockchip_pinctrl_get_soc_data()
600 int pin = 0; in rockchip_pinctrl_get_soc_data() local
[all …]
/u-boot/arch/mips/mach-jz47xx/jz4780/
A Dgpio.c13 int pin = gpio % 32; in jz47xx_gpio_get_value() local
15 return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin); in jz47xx_gpio_get_value()
22 int pin = gpio % 32; in jz47xx_gpio_direction_input() local
24 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); in jz47xx_gpio_direction_input()
25 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); in jz47xx_gpio_direction_input()
26 writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port)); in jz47xx_gpio_direction_input()
33 int pin = gpio % 32; in jz47xx_gpio_direction_output() local
35 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); in jz47xx_gpio_direction_output()
36 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); in jz47xx_gpio_direction_output()
37 writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port)); in jz47xx_gpio_direction_output()
[all …]
/u-boot/drivers/pinctrl/mscc/
A DKconfig10 bool "Microsemi ocelot family pin control driver"
12 Support pin multiplexing and pin configuration control on
19 bool "Microsemi luton family pin control driver"
21 Support pin multiplexing and pin configuration control on
28 bool "Microsemi jr2 family pin control driver"
30 Support pin multiplexing and pin configuration control on
37 bool "Microsemi servalt family pin control driver"
39 Support pin multiplexing and pin configuration control on
46 bool "Microsemi serval family pin control driver"
48 Support pin multiplexing and pin configuration control on
/u-boot/doc/device-tree-bindings/pinctrl/
A Dnexell,s5pxx18-pinctrl.txt34 - pin-function = Select the function for use in a selected pin.
51 - pin settings
54 pin-function = <1>;
55 pin-pull = <2>;
56 pin-strength = <2>;
61 pin-function = <1>;
62 pin-pull = <2>;
63 pin-strength = <1>;
68 pin-function = <1>;
69 pin-pull = <2>;
[all …]
/u-boot/arch/powerpc/include/asm/
A Diopin_8xx.h19 u_char pin:5; /* port pin (0-31) */ member
35 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
39 setbits_be32(datp, 1 << (31 - iopin->pin)); in iopin_set_high()
43 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
47 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
58 clrbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_low()
62 clrbits_be32(datp, 1 << (31 - iopin->pin)); in iopin_set_low()
66 clrbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_low()
70 clrbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_low()
129 setbits_be16(dirp, 1 << (15 - iopin->pin)); in iopin_set_out()
[all …]
/u-boot/drivers/misc/
A Dk3_esm.c35 value = readl(base + ESM_PIN_EN_SET_OFFSET(pin)); in esm_pin_enable()
36 value |= ESM_PIN_MASK(pin); in esm_pin_enable()
38 writel(value, base + ESM_PIN_EN_SET_OFFSET(pin)); in esm_pin_enable()
45 value = readl(base + ESM_INTR_EN_SET_OFFSET(pin)); in esm_intr_enable()
46 value |= ESM_INTR_MASK(pin); in esm_intr_enable()
48 writel(value, base + ESM_INTR_EN_SET_OFFSET(pin)); in esm_intr_enable()
55 value = readl(base + ESM_INTR_PRIO_SET_OFFSET(pin)); in esm_intr_prio_set()
56 value |= ESM_INTR_PRIO_MASK(pin); in esm_intr_prio_set()
65 value = readl(base + ESM_STS(pin)); in esm_clear_raw_status()
66 value |= ESM_STS_MASK(pin); in esm_clear_raw_status()
[all …]
/u-boot/arch/arm/include/asm/arch-sunxi/
A Dgpio.h83 #define GPIO_BANK(pin) ((pin) >> 5) argument
84 #define GPIO_NUM(pin) ((pin) & 0x1f) argument
86 #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) argument
87 #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) argument
89 #define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) argument
90 #define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) argument
92 #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) argument
93 #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) argument
223 int sunxi_gpio_get_cfgpin(u32 pin);
224 void sunxi_gpio_set_drv(u32 pin, u32 val);
[all …]
/u-boot/drivers/pinctrl/mtmips/
A DKconfig7 bool "MediaTek MT7620 pin control driver"
11 Support pin multiplexing control on MediaTek MT7620.
13 the pin mux functions for each available pin groups.
16 bool "MediaTek MT7621 pin control driver"
20 Support pin multiplexing control on MediaTek MT7621.
22 the pin mux functions for each available pin groups.
25 bool "MediaTek MT7628 pin control driver"
29 Support pin multiplexing control on MediaTek MT7628.
31 the pin mux functions for each available pin groups.
/u-boot/drivers/pinctrl/nexell/
A Dpinctrl-s5pxx18.c54 u32 reg = (pin / 16) ? GPIOX_ALTFN1 : GPIOX_ALTFN0; in nx_gpio_set_pad_function()
56 nx_gpio_set_bit2(base + reg, pin % 16, padfunc); in nx_gpio_set_pad_function()
68 nx_gpio_set_bit(base + GPIOX_PULLENB, pin, false); in nx_gpio_set_pull_mode()
69 nx_gpio_set_bit(base + GPIOX_PULLSEL, pin, false); in nx_gpio_set_pull_mode()
72 pin, (mode & 1 ? true : false)); in nx_gpio_set_pull_mode()
73 nx_gpio_set_bit(base + GPIOX_PULLENB, pin, true); in nx_gpio_set_pull_mode()
81 PULLUP_MASK = (1UL << pin); in nx_alive_set_pullup()
134 unsigned int count, idx, pin; in s5pxx18_pinctrl_set_state() local
159 reg = pin_to_bank_base(dev, name, &pin); in s5pxx18_pinctrl_set_state()
164 nx_alive_set_pullup((void *)reg, pin, in s5pxx18_pinctrl_set_state()
[all …]
/u-boot/arch/arm/mach-at91/include/mach/
A Dat91_pio.h130 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
131 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
132 int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
133 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
134 int at91_set_pio_output(unsigned port, unsigned pin, int value);
135 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
136 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
137 int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
138 int at91_set_pio_value(unsigned port, unsigned pin, int value);
139 int at91_get_pio_value(unsigned port, unsigned pin);
[all …]
/u-boot/drivers/pinctrl/mvebu/
A DKconfig5 bool "Armada 38x pin control driver"
7 Support pin multiplexing and pin configuration control on
12 bool "Armada 37xx pin control driver"
14 Support pin multiplexing and pin configuration control on
19 bool "Armada 7k/8k pin control driver"
21 Support pin multiplexing and pin configuration control on

Completed in 55 milliseconds

12345678910>>...23