| /u-boot/drivers/video/tegra124/ |
| A D | display.c | 31 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
52 refresh % 1000, timing->pixelclock.typ); in print_mode()
95 timing->pixelclock.typ, shift_clock_div); in update_display_mode()
311 printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ); in dump_config()
381 plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); in display_init()
385 } else if (plld_rate != timing->pixelclock.typ * 2) { in display_init()
387 timing->pixelclock.typ = plld_rate / 2; in display_init()
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| A D | dp.c | 509 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
513 if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >= in tegra_dc_dp_calc_config()
518 timing->pixelclock.typ)); in tegra_dc_dp_calc_config()
520 ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f; in tegra_dc_dp_calc_config()
623 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config()
639 * link_rate, timing->pixelclock.typ) - (36 / in tegra_dc_dp_calc_config()
1357 if (!timing->pixelclock.typ || !timing->hactive.typ || in tegra_dc_dp_explore_link_cfg()
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| /u-boot/drivers/video/ |
| A D | atmel_lcdfb.c | 78 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; in atmel_fb_init()
79 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) in atmel_fb_init()
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| A D | tdo-tl070wsh30.c | 23 .pixelclock.typ = 47250000,
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| A D | atmel_hlcdfb.c | 106 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
107 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
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| A D | mxsfb.c | 78 ret = clk_set_rate(&clk, timings->pixelclock.typ); in mxs_lcd_init()
113 mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000); in mxs_lcd_init()
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| A D | dw_mipi_dsi.c | 239 calc_val = timings->pixelclock.typ; in dsi_mode_vrefresh()
608 frac = lbcc % (timings->pixelclock.typ / 1000); in dw_mipi_dsi_get_hcomponent_lbcc()
609 lbcc = lbcc / (timings->pixelclock.typ / 1000); in dw_mipi_dsi_get_hcomponent_lbcc()
825 timings->pixelclock.typ = clk_get_rate(&clk); in dw_mipi_dsi_init()
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| A D | renesas-r69328.c | 55 .pixelclock.typ = 68000000,
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| A D | endeavoru-panel.c | 29 .pixelclock.typ = 63200000,
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| A D | renesas-r61307.c | 109 .pixelclock.typ = 62000000,
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| A D | dw_hdmi.c | 987 edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ); in dw_hdmi_enable()
991 ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); in dw_hdmi_enable()
1000 hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ); in dw_hdmi_enable()
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| A D | orisetech_otm8009a.c | 68 .pixelclock.typ = 29700000,
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| A D | raydium-rm68200.c | 81 .pixelclock.typ = 54000000,
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| /u-boot/drivers/video/ti/ |
| A D | tilcdc.c | 197 if (timing.pixelclock.typ > (LCDC_FMAX / 2)) { in tilcdc_probe()
199 timing.pixelclock.typ); in tilcdc_probe()
250 rate = tilcdc_set_pixel_clk_rate(dev, timing.pixelclock.typ); in tilcdc_probe()
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| A D | tilcdc-panel.c | 141 priv->info.bpp, priv->timing.pixelclock.typ); in tilcdc_panel_of_to_plat()
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| /u-boot/drivers/video/sunxi/ |
| A D | sunxi_lcd.c | 56 lcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000, in sunxi_lcd_enable()
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| A D | sunxi_dw_hdmi.c | 244 int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ); in sunxi_dw_hdmi_lcdc_init()
294 return timing->pixelclock.typ <= 297000000; in sunxi_dw_hdmi_mode_valid()
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| /u-boot/drivers/video/rockchip/ |
| A D | rk3288_mipi.c | 94 priv->pix_clk = timing->pixelclock.typ; in rk_mipi_enable()
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| A D | rk3399_mipi.c | 86 priv->pix_clk = timing->pixelclock.typ; in rk_display_enable()
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| A D | dw_mipi_dsi_rockchip.c | 518 mpclk = DIV_ROUND_UP(timings->pixelclock.typ, 1000); in dw_mipi_dsi_get_lane_mbps()
531 phy_mipi_dphy_get_default_config(timings->pixelclock.typ * 10 / 8, in dw_mipi_dsi_get_lane_mbps()
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| /u-boot/drivers/video/stm32/ |
| A D | stm32_ltdc.c | 566 rate = clk_set_rate(&pclk, timings.pixelclock.typ); in stm32_ltdc_probe()
569 timings.pixelclock.typ, rate); in stm32_ltdc_probe()
572 timings.pixelclock.typ, rate); in stm32_ltdc_probe()
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| /u-boot/common/ |
| A D | edid.c | 91 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); in decode_timing()
131 timing->pixelclock.typ, in decode_timing()
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| /u-boot/doc/device-tree-bindings/video/tilcdc/ |
| A D | tilcdc.txt | 18 - max-pixelclock: The maximum pixel clock that can be supported
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| /u-boot/test/dm/ |
| A D | test-fdt.c | 1102 ut_assert(timing.pixelclock.typ == 6500000); in dm_test_decode_display_timing()
1124 ut_assert(timing.pixelclock.typ == 9000000); in dm_test_decode_display_timing()
1146 ut_assert(timing.pixelclock.typ == 33500000); in dm_test_decode_display_timing()
1182 ut_assert(timing.pixelclock.typ == 6500000); in dm_test_decode_panel_timing()
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| /u-boot/include/ |
| A D | fdtdec.h | 885 struct timing_entry pixelclock; member
|