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Searched refs:prediv (Results 1 – 13 of 13) sorted by relevance

/u-boot/drivers/clk/starfive/
A Dclk-jh7110-pll.c55 .prediv = (_pd), \
90 .prediv = 0x24,
107 .prediv = 0x2c,
124 .prediv = 0x34,
186 PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv); in jh7110_pll_set_rate()
205 u32 prediv, fbdiv, postdiv1; in jh7110_pllx_recalc_rate() local
212 prediv = getbits_le32((ulong)pll->base + pll->offset->prediv, in jh7110_pllx_recalc_rate()
255 do_div(refclk, prediv * postdiv1); in jh7110_pllx_recalc_rate()
A Dclk.h20 u32 prediv; member
27 u32 prediv; member
/u-boot/arch/arm/mach-davinci/include/mach/
A Ddm365_lowlevel.h16 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
17 int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
A Dpll_defs.h19 unsigned int prediv; /* 0x114 */ member
A Dhardware.h205 dv_reg prediv; member
/u-boot/drivers/video/rockchip/
A Drk_mipi.c202 u64 prediv = 1; in rk_mipi_phy_enable() local
275 prediv = i; in rk_mipi_phy_enable()
279 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
280 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
284 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
287 test_data[0] = prediv - 1; in rk_mipi_phy_enable()
/u-boot/arch/arm/mach-keystone/
A Dclock.c282 unsigned long mult = 1, prediv = 1, output_div = 2; in pll_freq_get() local
291 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; in pll_freq_get()
300 ret = ret / prediv / output_div * mult; in pll_freq_get()
332 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; in pll_freq_get()
337 ret = ((ret / prediv) * mult) / output_div; in pll_freq_get()
/u-boot/drivers/clk/imx/
A Dclk-composite-8m.c60 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
66 *prediv = 1; in imx8m_clk_composite_compute_dividers()
74 *prediv = div1; in imx8m_clk_composite_compute_dividers()
/u-boot/arch/arm/mach-keystone/include/mach/
A Dclock_defs.h23 u32 prediv; /* 14 */ member
/u-boot/drivers/phy/rockchip/
A Dphy-rockchip-inno-dsidphy.c224 u8 prediv; member
371 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
398 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_dsidphy_mipi_mode_enable()
/u-boot/arch/arm/mach-davinci/
A Dda850_lowlevel.c86 &reg->prediv); in da850_pll_init()
/u-boot/drivers/clk/
A Dclk_versaclock.c310 unsigned int prediv, div; in vc5_pfd_recalc_rate() local
314 dm_i2c_read(vc5->i2c, VC5_VCO_CTRL_AND_PREDIV, (uchar *)&prediv, 1); in vc5_pfd_recalc_rate()
317 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) in vc5_pfd_recalc_rate()
/u-boot/drivers/ram/rockchip/
A Dsdram_rv1126.c536 u32 fbdiv, prediv, postdiv, postdiv_en; in phy_pll_set() local
544 prediv = 1; in phy_pll_set()
565 PHY_PREDIV_MASK << PHY_PREDIV_SHIFT, prediv); in phy_pll_set()

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